Lines Matching defs:Op0
481 Register Op0 = getRegForValue(I->getOperand(0));
482 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
503 Register ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, Imm,
519 ISDOpcode, Op0, Op1);
1526 Register Op0 = getRegForValue(I->getOperand(0));
1527 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
1532 updateValueMap(I, Op0);
1537 Register ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0);
1768 const Value *Op0 = EVI->getOperand(0);
1769 Type *AggTy = Op0->getType();
1773 DenseMap<const Value *, Register>::iterator I = FuncInfo.ValueMap.find(Op0);
1776 else if (isa<Instruction>(Op0))
1777 ResultReg = FuncInfo.InitializeRegForValue(Op0);
1954 unsigned FastISel::fastEmit_r(MVT, MVT, unsigned, unsigned /*Op0*/) {
1958 unsigned FastISel::fastEmit_rr(MVT, MVT, unsigned, unsigned /*Op0*/,
1972 unsigned FastISel::fastEmit_ri(MVT, MVT, unsigned, unsigned /*Op0*/,
1981 Register FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0,
2000 Register ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Imm);
2013 return fastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
2047 const TargetRegisterClass *RC, unsigned Op0) {
2051 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2055 .addReg(Op0);
2058 .addReg(Op0);
2068 const TargetRegisterClass *RC, unsigned Op0,
2073 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2078 .addReg(Op0)
2082 .addReg(Op0)
2092 const TargetRegisterClass *RC, unsigned Op0,
2097 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2103 .addReg(Op0)
2108 .addReg(Op0)
2119 const TargetRegisterClass *RC, unsigned Op0,
2124 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2128 .addReg(Op0)
2132 .addReg(Op0)
2142 const TargetRegisterClass *RC, unsigned Op0,
2147 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2151 .addReg(Op0)
2156 .addReg(Op0)
2187 const TargetRegisterClass *RC, unsigned Op0,
2192 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2197 .addReg(Op0)
2202 .addReg(Op0)
2229 Register FastISel::fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0,
2232 assert(Register::isVirtualRegister(Op0) &&
2234 const TargetRegisterClass *RC = MRI.getRegClass(Op0);
2235 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
2237 ResultReg).addReg(Op0, 0, Idx);
2243 Register FastISel::fastEmitZExtFromI1(MVT VT, unsigned Op0) {
2244 return fastEmit_ri(VT, VT, ISD::AND, Op0, 1);