Lines Matching defs:VirtReg
231 bool RAGreedy::LRE_CanEraseVirtReg(Register VirtReg) {
232 LiveInterval &LI = LIS->getInterval(VirtReg);
233 if (VRM->hasPhys(VirtReg)) {
241 // dump will show the right state for that VirtReg.
246 void RAGreedy::LRE_WillShrinkVirtReg(Register VirtReg) {
247 if (!VRM->hasPhys(VirtReg))
251 LiveInterval &LI = LIS->getInterval(VirtReg);
399 /// tryAssign - Try to assign VirtReg to an available register.
400 MCRegister RAGreedy::tryAssign(const LiveInterval &VirtReg,
407 if (!Matrix->checkInterference(VirtReg, *I)) {
421 if (Register Hint = MRI->getSimpleHint(VirtReg.reg()))
426 if (EvictAdvisor->canEvictHintInterference(VirtReg, PhysHint,
428 evictInterference(VirtReg, PhysHint, NewVRegs);
433 if (trySplitAroundHintReg(PhysHint, VirtReg, NewVRegs, Order))
438 SetOfBrokenHints.insert(&VirtReg);
450 MCRegister CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost, FixedRegisters);
458 bool RegAllocEvictionAdvisor::canReassign(const LiveInterval &VirtReg,
462 LiveIntervalUnion::Query SubQ(VirtReg, Matrix->getLiveUnions()[Unit]);
467 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix)) {
472 LLVM_DEBUG(dbgs() << "can reassign: " << VirtReg << " from "
481 /// evictInterference - Evict any interferring registers that prevent VirtReg
484 void RAGreedy::evictInterference(const LiveInterval &VirtReg,
487 // Make sure that VirtReg has a cascade number, and assign that cascade
490 unsigned Cascade = ExtraInfo->getOrAssignNewCascade(VirtReg.reg());
498 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit);
509 // The same VirtReg may be present in multiple RegUnits. Skip duplicates.
515 VirtReg.isSpillable() < Intf->isSpillable()) &&
534 RegAllocEvictionAdvisor::getOrderLimit(const LiveInterval &VirtReg,
541 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg());
577 /// @param VirtReg Currently unassigned virtual register.
579 /// @return Physreg to assign VirtReg, or 0.
580 MCRegister RAGreedy::tryEvict(const LiveInterval &VirtReg,
589 VirtReg, Order, CostPerUseLimit, FixedRegisters);
591 evictInterference(VirtReg, BestPhys, NewVRegs);
1063 MCRegister RAGreedy::tryRegionSplit(const LiveInterval &VirtReg,
1066 if (!TRI->shouldRegionSplitForVirtReg(*MF, VirtReg))
1086 unsigned BestCand = calculateRegionSplitCost(VirtReg, Order, BestCost,
1093 return doRegionSplit(VirtReg, BestCand, HasCompact, NewVRegs);
1174 unsigned RAGreedy::calculateRegionSplitCost(const LiveInterval &VirtReg,
1192 unsigned RAGreedy::doRegionSplit(const LiveInterval &VirtReg, unsigned BestCand,
1197 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
1232 // VirtReg has a physical Hint, this function tries to split VirtReg around
1235 const LiveInterval &VirtReg,
1238 // Split the VirtReg may generate COPY instructions in multiple cold basic
1245 if (ExtraInfo->getStage(VirtReg) >= RS_Split2)
1249 Register Reg = VirtReg.reg();
1251 // Compute the cost of assigning a non Hint physical register to VirtReg.
1262 // Check if VirtReg interferes with OtherReg after this COPY instruction.
1263 if (VirtReg.liveAt(LIS->getInstructionIndex(Instr).getRegSlot()))
1280 SA->analyze(&VirtReg);
1285 doRegionSplit(VirtReg, BestCand, false/*HasCompact*/, NewVRegs);
1296 unsigned RAGreedy::tryBlockSplit(const LiveInterval &VirtReg,
1299 assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed");
1300 Register Reg = VirtReg.reg();
1302 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
1383 /// VirtReg.
1385 const MachineInstr *MI, const LiveInterval &VirtReg,
1397 LaneBitmask ReadMask = getInstReadLaneMask(MRI, *TRI, *MI, VirtReg.reg());
1400 for (const LiveInterval::SubRange &S : VirtReg.subranges()) {
1417 unsigned RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
1420 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg());
1425 if (!VirtReg.hasSubRanges())
1432 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
1455 getNumAllocatableRegsForConstraints(MI, VirtReg.reg(), SuperRC,
1458 (!SplitSubClass && VirtReg.hasSubRanges() &&
1459 !readsLaneSubset(*MRI, MI, VirtReg, TRI, Use, TII))) {
1477 DebugVars->splitRegister(VirtReg.reg(), LREdit.regs(), *LIS);
1513 // We know that VirtReg is a continuous interval from FirstInstr to
1567 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
1570 unsigned RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
1599 // If VirtReg is live across any register mask operands, compute a list of
1602 if (Matrix->checkRegMaskInterference(VirtReg)) {
1606 // Constrain to VirtReg's live range.
1648 bool ProgressRequired = ExtraInfo->getStage(VirtReg) >= RS_Split2;
1667 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg))
1763 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
1772 DebugVars->splitRegister(VirtReg.reg(), LREdit.regs(), *LIS);
1798 /// trySplit - Try to split VirtReg or one of its interferences, making it
1800 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1801 unsigned RAGreedy::trySplit(const LiveInterval &VirtReg, AllocationOrder &Order,
1805 if (ExtraInfo->getStage(VirtReg) >= RS_Spill)
1809 if (LIS->intervalIsInOneMBB(VirtReg)) {
1812 SA->analyze(&VirtReg);
1813 Register PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
1816 return tryInstructionSplit(VirtReg, Order, NewVRegs);
1822 SA->analyze(&VirtReg);
1827 if (ExtraInfo->getStage(VirtReg) < RS_Split2) {
1828 MCRegister PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1834 return tryBlockSplit(VirtReg, Order, NewVRegs);
1863 /// interfere with \p VirtReg on \p PhysReg (or one of its aliases) may be
1867 /// for \p VirtReg.
1871 MCRegister PhysReg, const LiveInterval &VirtReg,
1873 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg());
1876 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit);
1887 // If Intf is done and sits on the same register class as VirtReg, it
1889 // VirtReg. However there are at least two exceptions.
1891 // If VirtReg has tied defs and Intf doesn't, then
1901 !(hasTiedDef(MRI, VirtReg.reg()) &&
1914 /// tryLastChanceRecoloring - Try to assign a color to \p VirtReg by recoloring
1916 /// Last chance recoloring chooses a color for \p VirtReg and recolors every
1945 /// \p Order defines the preferred allocation order for \p VirtReg.
1955 /// \return a physical register that can be used for VirtReg or ~0u if none
1957 unsigned RAGreedy::tryLastChanceRecoloring(const LiveInterval &VirtReg,
1963 if (!TRI->shouldUseLastChanceRecoloringForVirtReg(*MF, VirtReg))
1966 LLVM_DEBUG(dbgs() << "Try last chance recoloring for " << VirtReg << '\n');
1971 assert((ExtraInfo->getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) &&
1986 // Mark VirtReg as fixed, i.e., it will not be recolored pass this point in
1988 assert(!FixedRegisters.count(VirtReg.reg()));
1989 FixedRegisters.insert(VirtReg.reg());
1994 LLVM_DEBUG(dbgs() << "Try to assign: " << VirtReg << " to "
2000 if (Matrix->checkInterference(VirtReg, PhysReg) >
2010 if (!mayRecolorAllInterferences(PhysReg, VirtReg, RecoloringCandidates,
2017 // with VirtReg on PhysReg (or one of its aliases). Enqueue them for
2033 // Do as if VirtReg was assigned to PhysReg so that the underlying
2036 Matrix->assign(VirtReg, PhysReg);
2038 // VirtReg may be deleted during tryRecoloringCandidates, save a copy.
2039 Register ThisVirtReg = VirtReg.reg();
2051 // I.e., VirtReg must be unassigned.
2053 Matrix->unassign(VirtReg);
2057 // It is possible VirtReg will be deleted during tryRecoloringCandidates.
2064 LLVM_DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to "
2069 Matrix->unassign(VirtReg);
2156 MCRegister RAGreedy::selectOrSplit(const LiveInterval &VirtReg,
2163 selectOrSplitImpl(VirtReg, NewVRegs, FixedRegisters, RecolorStack);
2189 const LiveInterval &VirtReg, AllocationOrder &Order, MCRegister PhysReg,
2191 if (ExtraInfo->getStage(VirtReg) == RS_Spill && VirtReg.isSpillable()) {
2194 SA->analyze(&VirtReg);
2203 if (ExtraInfo->getStage(VirtReg) < RS_Split) {
2206 SA->analyze(&VirtReg);
2209 unsigned BestCand = calculateRegionSplitCost(VirtReg, Order, BestCost,
2216 doRegionSplit(VirtReg, BestCand, false/*HasCompact*/, NewVRegs);
2289 /// Using the register assigned to \p VirtReg, try to recolor
2290 /// all the live ranges that are copy-related with \p VirtReg.
2297 void RAGreedy::tryHintRecoloring(const LiveInterval &VirtReg) {
2304 Register Reg = VirtReg.reg();
2422 MCRegister RAGreedy::selectOrSplitImpl(const LiveInterval &VirtReg,
2430 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix);
2432 tryAssign(VirtReg, Order, NewVRegs, FixedRegisters)) {
2438 MCRegister CSRReg = tryAssignCSRFirstTime(VirtReg, Order, PhysReg,
2447 // Non empty NewVRegs means VirtReg has been split.
2451 LiveRangeStage Stage = ExtraInfo->getStage(VirtReg);
2453 << ExtraInfo->getCascade(VirtReg.reg()) << '\n');
2460 tryEvict(VirtReg, Order, NewVRegs, CostPerUseLimit,
2462 Register Hint = MRI->getSimpleHint(VirtReg.reg());
2463 // If VirtReg has a hint and that hint is broken record this
2469 SetOfBrokenHints.insert(&VirtReg);
2479 ExtraInfo->setStage(VirtReg, RS_Split);
2481 NewVRegs.push_back(VirtReg.reg());
2485 if (Stage < RS_Spill && !VirtReg.empty()) {
2486 // Try splitting VirtReg or interferences.
2488 Register PhysReg = trySplit(VirtReg, Order, NewVRegs, FixedRegisters);
2495 if (Stage >= RS_Done || !VirtReg.isSpillable()) {
2496 return tryLastChanceRecoloring(VirtReg, Order, NewVRegs, FixedRegisters,
2500 // Finally spill VirtReg itself.
2502 TRI->shouldUseDeferredSpillingForVirtReg(*MF, VirtReg)) &&
2503 ExtraInfo->getStage(VirtReg) < RS_Memory) {
2508 ExtraInfo->setStage(VirtReg, RS_Memory);
2510 NewVRegs.push_back(VirtReg.reg());
2514 LiveRangeEdit LRE(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);