Lines Matching defs:PhysReg
404 MCRegister PhysReg;
405 for (auto I = Order.begin(), E = Order.end(); I != E && !PhysReg; ++I) {
411 PhysReg = *I;
414 if (!PhysReg.isValid())
415 return PhysReg;
417 // PhysReg is available, but there may be a better choice.
442 uint8_t Cost = RegCosts[PhysReg.id()];
446 return PhysReg;
448 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << " is available at cost "
451 return CheapReg ? CheapReg : PhysReg;
485 MCRegister PhysReg,
492 LLVM_DEBUG(dbgs() << "evicting " << printReg(PhysReg, TRI)
497 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
523 /// Returns true if the given \p PhysReg is a callee saved register and has not
525 bool RegAllocEvictionAdvisor::isUnusedCalleeSavedReg(MCRegister PhysReg) const {
526 MCRegister CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg);
530 return !Matrix->isPhysRegUsed(PhysReg);
561 MCRegister PhysReg) const {
562 if (RegCosts[PhysReg.id()] >= CostPerUseLimit)
566 if (CostPerUseLimit == 1 && isUnusedCalleeSavedReg(PhysReg)) {
568 dbgs() << printReg(PhysReg, TRI) << " would clobber CSR "
569 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI)
768 if (Cand.PhysReg) {
820 // that all the through blocks have interference when PhysReg is unset.
1026 // - Candidate intervals can be assigned to Cand.PhysReg.
1097 RAGreedy::calculateRegionSplitCostAroundReg(MCPhysReg PhysReg,
1108 if (CandIndex == BestCand || !GlobalCand[CandIndex].PhysReg)
1125 Cand.reset(IntfCache, PhysReg);
1130 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tno positive bundles\n");
1133 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI)
1141 << printReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
1180 for (MCPhysReg PhysReg : Order) {
1181 assert(PhysReg);
1182 if (IgnoreCSR && EvictAdvisor->isUnusedCalleeSavedReg(PhysReg))
1185 calculateRegionSplitCostAroundReg(PhysReg, Order, BestCost, NumCands,
1209 LLVM_DEBUG(dbgs() << "Split for " << printReg(Cand.PhysReg, TRI) << " in "
1218 assert(!Cand.PhysReg && "Compact region has no physreg");
1488 /// in order to use PhysReg between two entries in SA->UseSlots.
1492 void RAGreedy::calcGapWeights(MCRegister PhysReg,
1508 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
1543 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
1660 for (MCPhysReg PhysReg : Order) {
1661 assert(PhysReg);
1663 // order to make use of PhysReg between UseSlots[I] and UseSlots[I + 1].
1664 calcGapWeights(PhysReg, GapWeight);
1667 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg))
1686 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << ' ' << Uses[SplitBefore]
1813 Register PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
1814 if (PhysReg || !NewVRegs.empty())
1815 return PhysReg;
1828 MCRegister PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1829 if (PhysReg || !NewVRegs.empty())
1830 return PhysReg;
1851 /// same, as \p PhysReg.
1854 MCRegister PhysReg,
1857 if (PhysReg == AssignedReg)
1859 return TRI.regsOverlap(PhysReg, AssignedReg);
1863 /// interfere with \p VirtReg on \p PhysReg (or one of its aliases) may be
1864 /// recolored to free \p PhysReg.
1866 /// the live intervals that need to be recolored in order to free \p PhysReg
1871 MCRegister PhysReg, const LiveInterval &VirtReg,
1875 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
1900 !assignedRegPartiallyOverlaps(*TRI, *VRM, PhysReg, *Intf)) &&
1992 for (MCRegister PhysReg : Order) {
1993 assert(PhysReg.isValid());
1995 << printReg(PhysReg, TRI) << '\n');
2000 if (Matrix->checkInterference(VirtReg, PhysReg) >
2008 // Early give up on this PhysReg if it is obvious we cannot recolor all
2010 if (!mayRecolorAllInterferences(PhysReg, VirtReg, RecoloringCandidates,
2017 // with VirtReg on PhysReg (or one of its aliases). Enqueue them for
2033 // Do as if VirtReg was assigned to PhysReg so that the underlying
2036 Matrix->assign(VirtReg, PhysReg);
2054 return PhysReg;
2065 << printReg(PhysReg, TRI) << '\n');
2089 MCRegister PhysReg;
2090 std::tie(LI, PhysReg) = RecolorStack[I];
2098 MCRegister PhysReg;
2099 std::tie(LI, PhysReg) = RecolorStack[I];
2101 Matrix->assign(*LI, PhysReg);
2128 MCRegister PhysReg = selectOrSplitImpl(*LI, NewVRegs, FixedRegisters,
2134 if (PhysReg == ~0u || (!PhysReg && !LI->empty()))
2137 if (!PhysReg) {
2144 << " succeeded with: " << printReg(PhysReg, TRI) << '\n');
2146 Matrix->assign(*LI, PhysReg);
2189 const LiveInterval &VirtReg, AllocationOrder &Order, MCRegister PhysReg,
2196 return PhysReg;
2213 return PhysReg;
2219 return PhysReg;
2277 /// \p PhysReg was used.
2278 /// \return The cost of \p List for \p PhysReg.
2280 MCRegister PhysReg) {
2283 if (Info.PhysReg != PhysReg)
2299 // reusing PhysReg for the copy-related live-ranges. Indeed, we evicted
2300 // some register and PhysReg may be available for the other live-ranges.
2305 MCRegister PhysReg = VRM->getPhys(Reg);
2312 << '(' << printReg(PhysReg, TRI) << ")\n");
2334 if (CurrPhys != PhysReg && (!MRI->getRegClass(Reg)->contains(PhysReg) ||
2335 Matrix->checkInterference(LI, PhysReg)))
2346 if (CurrPhys != PhysReg) {
2349 BlockFrequency NewCopiesCost = getBrokenHintFreq(Info, PhysReg);
2363 Matrix->assign(LI, PhysReg);
2431 if (MCRegister PhysReg =
2437 EvictAdvisor->isUnusedCalleeSavedReg(PhysReg) && NewVRegs.empty()) {
2438 MCRegister CSRReg = tryAssignCSRFirstTime(VirtReg, Order, PhysReg,
2445 return PhysReg;
2459 if (Register PhysReg =
2468 if (Hint && Hint != PhysReg)
2470 return PhysReg;
2488 Register PhysReg = trySplit(VirtReg, Order, NewVRegs, FixedRegisters);
2489 if (PhysReg || (NewVRegs.size() - NewVRegSizeBefore))
2490 return PhysReg;