Lines Matching defs:DefOp

676   unsigned DefOp;
679   DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp)
680     : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {}
689     DefOp = DefMO->getOperandNo();
782   for (unsigned DefOp : LiveDefOps) {
784          TRI->regunits(UseMI->getOperand(DefOp).getReg().asMCReg())) {
787       LRU.Op = DefOp;
845         .computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI, Dep.UseOp);
996     UseHeight += SchedModel.computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI,
1012 /// Assuming that the virtual register defined by DefMI:DefOp was used by
1016 addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
1019   Register Reg = DefMI->getOperand(DefOp).getReg();
1122             addLiveIns(Deps.front().DefMI, Deps.front().DefOp, Stack);
1152           addLiveIns(Dep.DefMI, Dep.DefOp, Stack);
1223     DepCycle += TE.MTM.SchedModel.computeOperandLatency(Dep.DefMI, Dep.DefOp,