Lines Matching defs:SUnits

570   DDG = std::make_unique<SwingSchedulerDDG>(SUnits, &EntrySU, &ExitSU);
840   for (auto &SU : SUnits) {
937   for (SUnit &I : SUnits) {
1019   for (SUnit &I : SUnits) {
1590   BitVector Added(SUnits.size());
1592   for (int i = 0, e = SUnits.size(); i != e; ++i) {
1595     for (auto &OE : DAG->DDG->getOutEdges(&SUnits[i])) {
1629     for (auto &IE : DAG->DDG->getInEdges(&SUnits[i])) {
1656   SUnit *SV = &SUnits[V];
1710   Circuits Cir(SUnits, Topo);
1713   for (int I = 0, E = SUnits.size(); I != E; ++I) {
1738   for (SUnit &SU : DAG->SUnits) {
1806   ScheduleInfo.resize(SUnits.size());
1810       const SUnit &SU = SUnits[I];
1820     SUnit *SU = &SUnits[I];
1840     SUnit *SU = &SUnits[I];
1863     for (unsigned i = 0; i < SUnits.size(); i++) {
1865       dbgs() << "\t   ASAP = " << getASAP(&SUnits[i]) << "\n";
1866       dbgs() << "\t   ALAP = " << getALAP(&SUnits[i]) << "\n";
1867       dbgs() << "\t   MOV  = " << getMOV(&SUnits[i]) << "\n";
1868       dbgs() << "\t   D    = " << getDepth(&SUnits[i]) << "\n";
1869       dbgs() << "\t   H    = " << getHeight(&SUnits[i]) << "\n";
1870       dbgs() << "\t   ZLD  = " << getZeroLatencyDepth(&SUnits[i]) << "\n";
1871       dbgs() << "\t   ZLH  = " << getZeroLatencyHeight(&SUnits[i]) << "\n";
2028     std::vector<SUnit *> SUnits(NS.begin(), NS.end());
2029     llvm::sort(SUnits, [](const SUnit *A, const SUnit *B) {
2033     for (auto &SU : SUnits) {
2158   for (SUnit &SU : SUnits) {
3121   for (auto &SU : SSD->SUnits)
3151   for (SUnit &SU : SSD->SUnits) {
3196   for (SUnit &SU : SSD->SUnits) {
3403   for (const SUnit &SU : SSD->SUnits)
3607   for (SUnit &SU : DAG->SUnits)
3612   for (SUnit &SU : DAG->SUnits)
3673   for (SUnit &SU : DAG->SUnits) {
3799 SwingSchedulerDDG::SwingSchedulerDDG(std::vector<SUnit> &SUnits, SUnit *EntrySU,
3802   EdgesVec.resize(SUnits.size());
3806   for (auto &SU : SUnits)