Lines Matching defs:SSD

1081 static void computeScheduledInsts(const SwingSchedulerDAG *SSD,
1102     CycleInstrs = Schedule.reorderInstructions(SSD, CycleInstrs);
1512   bool detect(const SwingSchedulerDAG *SSD, SMSchedule &Schedule,
1519     computeScheduledInsts(SSD, Schedule, OrderedInsts, Stages);
2925 void SMSchedule::orderDependence(const SwingSchedulerDAG *SSD, SUnit *SU,
2934   const SwingSchedulerDDG *DDG = SSD->getDDG();
2947           if (unsigned NewReg = SSD->getInstrBaseReg(SU))
2983                  isLoopCarriedDefOfUse(SSD, (*I)->getInstr(), MO)) {
3042     orderDependence(SSD, UseSU, Insts);
3043     orderDependence(SSD, SU, Insts);
3044     orderDependence(SSD, DefSU, Insts);
3056 bool SMSchedule::isLoopCarried(const SwingSchedulerDAG *SSD,
3061   SUnit *DefSU = SSD->getSUnit(&Phi);
3068   SUnit *UseSU = SSD->getSUnit(MRI.getVRegDef(LoopVal));
3085 bool SMSchedule::isLoopCarriedDefOfUse(const SwingSchedulerDAG *SSD,
3095   if (!isLoopCarried(SSD, *Phi))
3117     SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI) {
3121   for (auto &SU : SSD->SUnits)
3125   const SwingSchedulerDDG *DDG = SSD->getDDG();
3147     SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI) {
3148   SmallSet<SUnit *, 8> DNP = computeUnpipelineableNodes(SSD, PLI);
3151   for (SUnit &SU : SSD->SUnits) {
3161     for (const auto &IE : SSD->getDDG()->getInEdges(&SU))
3167     for (auto &OE : SSD->getDDG()->getOutEdges(&SU))
3195 bool SMSchedule::isValidSchedule(SwingSchedulerDAG *SSD) {
3196   for (SUnit &SU : SSD->SUnits) {
3202     for (auto &OE : SSD->getDDG()->getOutEdges(&SU)) {
3365 SMSchedule::reorderInstructions(const SwingSchedulerDAG *SSD,
3375       orderDependence(SSD, SU, NewOrderI);
3384 void SMSchedule::finalizeSchedule(SwingSchedulerDAG *SSD) {
3403   for (const SUnit &SU : SSD->SUnits)
3404     SSD->applyInstrChange(SU.getInstr(), *this);
3410     cycleInstrs = reorderInstructions(SSD, cycleInstrs);
3411     SSD->fixupRegisterOverlaps(cycleInstrs);