Lines Matching defs:Dep

882               SDep Dep(Load, SDep::Barrier);
883               Dep.setLatency(1);
884               SU.addPred(Dep);
892             SDep Dep(Load, SDep::Barrier);
893             Dep.setLatency(1);
894             SU.addPred(Dep);
900             SDep Dep(Load, SDep::Barrier);
901             Dep.setLatency(1);
902             SU.addPred(Dep);
907             SDep Dep(Load, SDep::Barrier);
908             Dep.setLatency(1);
909             SU.addPred(Dep);
916             SDep Dep(Load, SDep::Barrier);
917             Dep.setLatency(1);
918             SU.addPred(Dep);
958               SDep Dep(SU, SDep::Anti, Reg);
959               Dep.setLatency(1);
960               I.addPred(Dep);
978             SDep Dep(SU, SDep::Data, Reg);
979             Dep.setLatency(0);
980             ST.adjustSchedDependency(SU, 0, &I, MO.getOperandNo(), Dep,
982             I.addPred(Dep);
1066     SDep Dep(&I, SDep::Anti, NewBase);
1068     LastSU->addPred(Dep);
1601         auto Dep = OutputDeps.find(BackEdge);
1602         if (Dep != OutputDeps.end()) {
1603           BackEdge = Dep->second;
1604           OutputDeps.erase(Dep);
1724 // PHI-------Anti-Dep-----> COPY/REG_SEQUENCE (loop-carried)
1725 // SRCOfCopY------True-Dep---> COPY/REG_SEQUENCE
1726 // PHI-------True-Dep------> USEOfPhi
1729 // USEOfPHI -------Artificial-Dep---> SRCOfCopy
1748     for (auto &Dep : SU.Preds) {
1749       SUnit *TmpSU = Dep.getSUnit();
1751       SDep::Kind DepKind = Dep.getKind();
1769       for (auto &Dep : PHISUs[Index]->Succs) {
1770         if (Dep.getKind() != SDep::Data)
1773         SUnit *TmpSU = Dep.getSUnit();
2814 int SMSchedule::earliestCycleInChain(const SwingSchedulerDDGEdge &Dep,
2818   Worklist.push_back(Dep);
2838 int SMSchedule::latestCycleInChain(const SwingSchedulerDDGEdge &Dep,
2842   Worklist.push_back(Dep);
2911       for (const auto &Dep : SU->Preds) {
2914         if (BE && Dep.getSUnit() == BE && !SU->getInstr()->isPHI() &&