Lines Matching full:feature

5 // MCPU-ROCKET32: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
9 // MCPU-ROCKET64: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
13 // MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+c"
14 // MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
19 // MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+m" "-target-feature" "+c"
20 // MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
25 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
26 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+c"
27 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zicbom" "-target-feature" "+zicboz" "-target-feature" "+zicsr" "-target-feature" "+zifencei"
28 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" "-target-feature" "+zbc"
29 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zbkb" "-target-feature" "+zbkc" "-target-feature" "+zbkx" "-target-feature" "+zbs"
30 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zkn" "-target-feature" "+zknd" "-target-feature" "+zkne" "-target-feature" "+zknh"
31 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
36 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+m"
37 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+a"
38 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+f"
39 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+d"
40 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+c"
41 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+v"
42 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zic64b"
43 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicbom"
44 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicbop"
45 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicboz"
46 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccamoa"
47 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccif"
48 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicclsm"
49 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccrse"
50 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicntr"
51 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicond"
52 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicsr"
53 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zifencei"
54 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zihintpause"
55 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zihpm"
56 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+za64rs"
57 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zfh"
58 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zfhmin"
59 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zba"
60 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbb"
61 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbc"
62 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbkc"
63 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbs"
64 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zkt"
65 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve32f"
66 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve32x"
67 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64d"
68 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64f"
69 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64x"
70 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvfh"
71 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvfhmin"
72 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvkt"
73 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl128b"
74 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl256b"
75 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl32b"
76 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl64b"
77 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ssccptr"
78 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sscofpmf"
79 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sscounterenw"
80 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstc"
81 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstvala"
82 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstvecd"
83 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svade"
84 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svbare"
85 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svinval"
86 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svnapot"
87 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svpbmt"
106 // MCPU-MIPS-P8700-SAME: "-target-feature" "+m"
107 // MCPU-MIPS-P8700-SAME: "-target-feature" "+a"
108 // MCPU-MIPS-P8700-SAME: "-target-feature" "+f"
109 // MCPU-MIPS-P8700-SAME: "-target-feature" "+d"
110 // MCPU-MIPS-P8700-SAME: "-target-feature" "+c"
111 // MCPU-MIPS-P8700-SAME: "-target-feature" "+zicsr"
112 // MCPU-MIPS-P8700-SAME: "-target-feature" "+zifencei"
113 // MCPU-MIPS-P8700-SAME: "-target-feature" "+zaamo"
114 // MCPU-MIPS-P8700-SAME: "-target-feature" "+zalrsc"
115 // MCPU-MIPS-P8700-SAME: "-target-feature" "+zba"
116 // MCPU-MIPS-P8700-SAME: "-target-feature" "+zbb"
129 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+m"
130 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+a"
131 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+f"
132 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+d"
133 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+c"
134 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+v"
135 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+h"
136 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicbom"
137 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicbop"
138 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicboz"
139 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicntr"
140 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicond"
141 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicsr"
142 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zifencei"
143 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintntl"
144 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintpause"
145 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihpm"
146 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zimop"
147 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zmmul"
148 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zawrs"
149 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfa"
150 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfbfmin"
151 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfh"
152 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfhmin"
153 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zca"
154 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zcb"
155 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zba"
156 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zbb"
157 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zbs"
158 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zkt"
159 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvbb"
160 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvbc"
161 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve32f"
162 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve32x"
163 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64d"
164 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64f"
165 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64x"
166 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfbfmin"
167 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfbfwma"
168 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfh"
169 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfhmin"
170 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkb"
171 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkg"
172 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkn"
173 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvknc"
174 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkned"
175 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkng"
176 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvknhb"
177 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkt"
178 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl128b"
179 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl256b"
180 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl32b"
181 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl64b"
182 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svinval"
183 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svnapot"
184 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svpbmt"
188 // MCPU-VEYRON-V1: "-target-feature" "+m"
189 // MCPU-VEYRON-V1: "-target-feature" "+a"
190 // MCPU-VEYRON-V1: "-target-feature" "+f"
191 // MCPU-VEYRON-V1: "-target-feature" "+d"
192 // MCPU-VEYRON-V1: "-target-feature" "+c"
193 // MCPU-VEYRON-V1: "-target-feature" "+zicbom"
194 // MCPU-VEYRON-V1: "-target-feature" "+zicbop"
195 // MCPU-VEYRON-V1: "-target-feature" "+zicboz"
196 // MCPU-VEYRON-V1: "-target-feature" "+zicntr"
197 // MCPU-VEYRON-V1: "-target-feature" "+zicsr"
198 // MCPU-VEYRON-V1: "-target-feature" "+zifencei"
199 // MCPU-VEYRON-V1: "-target-feature" "+zihintpause"
200 // MCPU-VEYRON-V1: "-target-feature" "+zihpm"
201 // MCPU-VEYRON-V1: "-target-feature" "+zba"
202 // MCPU-VEYRON-V1: "-target-feature" "+zbb"
203 // MCPU-VEYRON-V1: "-target-feature" "+zbc"
204 // MCPU-VEYRON-V1: "-target-feature" "+zbs"
205 // MCPU-VEYRON-V1: "-target-feature" "+xventanacondops"
234 // MCPU-SIFIVE-E20: "-target-feature" "+m" "-target-feature" "+c"
235 // MCPU-SIFIVE-E20: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
241 // MCPU-SIFIVE-E21: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+c"
242 // MCPU-SIFIVE-E21: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
248 // MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f"
249 // MCPU-SIFIVE-E24: "-target-feature" "+c"
250 // MCPU-SIFIVE-E24: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
256 // MCPU-SIFIVE-E34: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f"
257 // MCPU-SIFIVE-E34: "-target-feature" "+c"
258 // MCPU-SIFIVE-E34: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
264 // MCPU-ABI-SIFIVE-S21: "-target-feature" "+m" "-target-feature" "+a"
265 // MCPU-ABI-SIFIVE-S21: "-target-feature" "+c"
266 // MCPU-ABI-SIFIVE-S21: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
272 // MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a"
273 // MCPU-ABI-SIFIVE-S51: "-target-feature" "+c"
274 // MCPU-ABI-SIFIVE-S51: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
280 // MCPU-SIFIVE-S54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
281 // MCPU-SIFIVE-S54: "-target-feature" "+c"
282 // MCPU-SIFIVE-S54: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
288 // MCPU-SIFIVE-S76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
289 // MCPU-SIFIVE-S76: "-target-feature" "+c"
290 // MCPU-SIFIVE-S76: "-target-feature" "+zicsr" "-target-feature" "+zifencei" "-target-feature" "+zihintpause"
296 // MCPU-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
297 // MCPU-SIFIVE-U54: "-target-feature" "+c"
298 // MCPU-SIFIVE-U54: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
304 // MCPU-ABI-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
305 // MCPU-ABI-SIFIVE-U54: "-target-feature" "+c"
306 // MCPU-ABI-SIFIVE-U54: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
312 // MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f"
313 // MCPU-SIFIVE-E76: "-target-feature" "+c"
314 // MCPU-SIFIVE-E76: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
320 // MCPU-ABI-SIFIVE-U74: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
321 // MCPU-ABI-SIFIVE-U74: "-target-feature" "+c"
322 // MCPU-ABI-SIFIVE-U74: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
327 // MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31" "-target-feature" "+m" "-target-feature" "+c"
331 // target feature, but mcpu will.
338 // MTUNE-E31-MCPU-E76-NOT: "-target-feature" "+f"
339 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+m"
340 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+a"
341 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+c"
342 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
348 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
349 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+c" "-target-feature" "+v"
350 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
351 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh"
352 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
353 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvfh"
354 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl128b"
355 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl256b" "-target-feature" "+zvl32b"
356 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" "+zvl64b"
361 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+m"
362 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+a"
363 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+f"
364 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+d"
365 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+c"
366 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zic64b"
367 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicbom"
368 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicbop"
369 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicboz"
370 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+ziccamoa"
371 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+ziccif"
372 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicclsm"
373 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+ziccrse"
374 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicntr"
375 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicsr"
376 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zifencei"
377 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zihintntl"
378 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zihintpause"
379 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zihpm"
380 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+za64rs"
381 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zfhmin"
382 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zba"
383 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbb"
384 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
389 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+m"
390 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+a"
391 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+f"
392 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+d"
393 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+c"
394 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+v"
395 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zic64b"
396 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicbom"
397 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicbop"
398 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicboz"
399 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccamoa"
400 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccif"
401 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicclsm"
402 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccrse"
403 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicntr"
404 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicsr"
405 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zifencei"
406 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihintntl"
407 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihintpause"
408 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihpm"
409 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zmmul"
410 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+za64rs"
411 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zfhmin"
412 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zba"
413 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zbb"
414 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zbs"
415 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvbb"
416 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvbc"
417 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve32f"
418 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve32x"
419 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve64d"
420 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve64f"
421 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve64x"
422 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkg"
423 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkn"
424 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvknc"
425 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkned"
426 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkng"
427 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvknhb"
428 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvks"
429 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksc"
430 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksed"
431 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksg"
432 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksh"
433 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkt"
438 // MCPU-SIFIVE-P550-SAME: "-target-feature" "+m"
439 // MCPU-SIFIVE-P550-SAME: "-target-feature" "+a"
440 // MCPU-SIFIVE-P550-SAME: "-target-feature" "+f"
441 // MCPU-SIFIVE-P550-SAME: "-target-feature" "+d"
442 // MCPU-SIFIVE-P550-SAME: "-target-feature" "+c"
443 // MCPU-SIFIVE-P550-SAME: "-target-feature" "+zicsr"
444 // MCPU-SIFIVE-P550-SAME: "-target-feature" "+zifencei"
445 // MCPU-SIFIVE-P550-SAME: "-target-feature" "+zba"
446 // MCPU-SIFIVE-P550-SAME: "-target-feature" "+zbb"
451 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+m"
452 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+a"
453 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+f"
454 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+d"
455 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+c"
456 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+v"
457 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zic64b"
458 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicbom"
459 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicbop"
460 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicboz"
461 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+ziccamoa"
462 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+ziccif"
463 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicclsm"
464 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+ziccrse"
465 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicntr"
466 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicsr"
467 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zifencei"
468 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zihintntl"
469 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zihintpause"
470 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zihpm"
471 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+za64rs"
472 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zfhmin"
473 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zba"
474 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zbb"
475 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zbs"
476 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvbb"
477 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvbc"
478 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve32f"
479 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve32x"
480 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve64d"
481 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve64f"
482 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve64x"
483 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkg"
484 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkn"
485 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvknc"
486 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkned"
487 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkng"
488 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvknhb"
489 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvks"
490 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvksc"
491 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvksed"
492 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvksg"
493 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvksh"
494 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkt"
499 // MCPU-HAZARD3-SAME: "-target-feature" "+m"
500 // MCPU-HAZARD3-SAME: "-target-feature" "+a"
501 // MCPU-HAZARD3-SAME: "-target-feature" "+c"
502 // MCPU-HAZARD3-SAME: "-target-feature" "+zicsr"
503 // MCPU-HAZARD3-SAME: "-target-feature" "+zifencei"
504 // MCPU-HAZARD3-SAME: "-target-feature" "+zcb"
505 // MCPU-HAZARD3-SAME: "-target-feature" "+zcmp"
506 // MCPU-HAZARD3-SAME: "-target-feature" "+zba"
507 // MCPU-HAZARD3-SAME: "-target-feature" "+zbb"
508 // MCPU-HAZARD3-SAME: "-target-feature" "+zbkb"
509 // MCPU-HAZARD3-SAME: "-target-feature" "+zbs"
522 // MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+m"
523 // MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+c"
524 // MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+zicsr"
525 // MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+zifencei"
533 // MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+m"
534 // MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+a"
535 // MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+c"
536 // MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+zicsr"
537 // MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+zifencei"
545 // MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-feature" "+m"
546 // MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-feature" "+f"
547 // MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-feature" "+d"
548 // MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-feature" "+c"
549 // MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-feature" "+zicsr"
550 // MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-feature" "+zifencei"
558 // MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+m"
559 // MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+a"
560 // MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+f"
561 // MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+d"
562 // MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+c"
563 // MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+zicsr"
564 // MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+zifencei"
572 // MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+m"
573 // MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+a"
574 // MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+f"
575 // MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+d"
576 // MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+c"
577 // MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+zicsr"
578 // MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+zifencei"
586 // MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+m"
587 // MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+a"
588 // MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+f"
589 // MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+d"
590 // MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+c"
591 // MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+zicsr"
592 // MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+zifencei"
600 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+m"
601 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+a"
602 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+f"
603 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+d"
604 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+c"
605 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+v"
606 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zicsr"
607 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zifencei"
608 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zba"
609 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbb"
610 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbc"
611 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkb"
612 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkc"
613 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkx"
614 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbs"
615 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zkn"
616 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zknd"
617 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zkne"
618 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zknh"