74 	return fbc->state_cache.plane.y - fbc->state_cache.plane.adjusted_y;  in get_crtc_fence_y_offset()
86 		*width = cache->plane.src_w;  in intel_fbc_get_plane_source_size()
88 		*height = cache->plane.src_h;  in intel_fbc_get_plane_source_size()
154 		fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane);  in i8xx_fbc_activate()
180 	dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN;  in g4x_fbc_activate()
227 	dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane);  in ilk_fbc_activate()
309 		dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);  in gen7_fbc_activate()
730 	effective_w += fbc->state_cache.plane.adjusted_x;  in intel_fbc_hw_tracking_covers_screen()
731 	effective_h += fbc->state_cache.plane.adjusted_y;  in intel_fbc_hw_tracking_covers_screen()
751 	cache->plane.rotation = plane_state->base.rotation;  in intel_fbc_update_state_cache()
757 	cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;  in intel_fbc_update_state_cache()
758 	cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;  in intel_fbc_update_state_cache()
759 	cache->plane.visible = plane_state->base.visible;  in intel_fbc_update_state_cache()
760 	cache->plane.adjusted_x = plane_state->main.x;  in intel_fbc_update_state_cache()
761 	cache->plane.adjusted_y = plane_state->main.y;  in intel_fbc_update_state_cache()
762 	cache->plane.y = plane_state->base.src.y1 >> 16;  in intel_fbc_update_state_cache()
764 	if (!cache->plane.visible)  in intel_fbc_update_state_cache()
815 	    cache->plane.rotation != DRM_MODE_ROTATE_0) {  in intel_fbc_can_activate()
893 	params->crtc.plane = crtc->plane;  in intel_fbc_get_reg_params()
902 		params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w,  in intel_fbc_get_reg_params()
1060 	struct drm_plane *plane;  in intel_fbc_choose_crtc()  local
1079 	for_each_new_plane_in_state(state, plane, plane_state, i) {  in intel_fbc_choose_crtc()
1091 		if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A)  in intel_fbc_choose_crtc()