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0dd6b0da |
| 17-Mar-2019 |
visa <visa@openbsd.org> |
Let each interrupt controller driver choose how to implement intr_barrier(9).
With this change, the barrier should finally work properly with cnmac(4) interrupts that have been assigned to secondary
Let each interrupt controller driver choose how to implement intr_barrier(9).
With this change, the barrier should finally work properly with cnmac(4) interrupts that have been assigned to secondary cores.
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cae6d111 |
| 17-Mar-2019 |
visa <visa@openbsd.org> |
Move intr_barrier(9) to the platform level so that it can be customized.
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a12b3618 |
| 16-Mar-2019 |
visa <visa@openbsd.org> |
Unify the top-level structure of interrupt handles. This helps when implementing interrupt-specific logic for intr_barrier(9).
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89182934 |
| 18-Jun-2017 |
visa <visa@openbsd.org> |
Split octeon interrupt code into a glue layer and a CIU driver. This makes possible to add drivers for other interrupt controllers on the platform.
The glue layer has been derived from arm64/armv7.
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aec33009 |
| 18-Jun-2017 |
visa <visa@openbsd.org> |
Move IPI control entry points into octeon_intr.c. Needed by upcoming driver changes.
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e6dd8ec3 |
| 06-Apr-2017 |
visa <visa@openbsd.org> |
Extend the fdt interrupt API a little.
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207b97a1 |
| 08-Dec-2016 |
visa <visa@openbsd.org> |
Add a routine for setting up interrupt handlers using fdt.
ok kettenis@
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7706e62d |
| 04-Dec-2016 |
visa <visa@openbsd.org> |
Add handling for the second interrupt bank. Needed by an upcoming driver.
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fe5d9ffb |
| 03-Dec-2016 |
visa <visa@openbsd.org> |
Implement octeon_intr_disestablish().
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fa4053fc |
| 02-Dec-2016 |
visa <visa@openbsd.org> |
Drop stale prototypes and an outdated comment.
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04a83ade |
| 02-Dec-2016 |
visa <visa@openbsd.org> |
Simplify interrupt dispatching by processing requests without prioritization by IPL.
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69084b88 |
| 20-Nov-2016 |
visa <visa@openbsd.org> |
Drop pointless type casts.
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f177a60a |
| 16-Jul-2016 |
visa <visa@openbsd.org> |
Add $OpenBSD$ / replace $Id$ with $OpenBSD$.
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b43ebd13 |
| 06-Mar-2016 |
mpi <mpi@openbsd.org> |
Rename mips64's trap_frame into trapframe.
For coherency with other archs and in order to use it in MI code.
ok visa@, tobiasu@
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289e3a2f |
| 26-Sep-2015 |
visa <visa@openbsd.org> |
xheart_splx() has to restore the interrupt mask even on secondary CPUs because each core has a separate mask. Otherwise the IPI can be left disabled accidentally on a non-primary CPU when the core us
xheart_splx() has to restore the interrupt mask even on secondary CPUs because each core has a separate mask. Otherwise the IPI can be left disabled accidentally on a non-primary CPU when the core uses the rendezvous mutex:
1. splraise(IPL_IPI) soft-masks the IPI.
2. An IPI hits and the CPU enters the interrupt handler.
3. The handler hard-masks the IPI.
4. The interrupt is not processed because of the CPU's current IPL. The IPI is left hard-masked on leaving the handler.
5. splx(s) lowers the IPL below IPL_IPI. However, the interrupt's hardware mask is left unchanged because of the CPU_IS_PRIMARY() check in xheart_splx().
After this, the system will eventually hang because the CPU does not respond to IPI requests of other cores.
While here, fix a similar situation with CIU interrupts on octeon. This might save a few moments of debugging once non-primary CPUs are allowed to process CIU interrupts.
ok miod@
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11b47dfe |
| 26-Sep-2015 |
visa <visa@openbsd.org> |
Let MP-safe interrupt handlers run without the kernel lock on octeon.
ok kettenis@
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989cf5dc |
| 01-May-2015 |
miod <miod@openbsd.org> |
Do not grab the kernel lock for clock interrupts. Help and ok kettenis@
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1b2dfb44 |
| 30-Sep-2014 |
jmatthew <jmatthew@openbsd.org> |
implement atomic operations using ll/sc, and convert rw_cas and callers of the pre-existing atomics to match.
tested on sgi (octane) and octeon (erl) ok miod@ dlg@
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a81120d9 |
| 02-Jun-2013 |
jasper <jasper@openbsd.org> |
move octeonreg.h to a more generic location and add multiple inclusion guards while here.
ok uebayasi@
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88f5258b |
| 03-Oct-2012 |
miod <miod@openbsd.org> |
Don't include <mips64/archtype.h> when you don't need it.
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7b6ae6a5 |
| 03-Oct-2012 |
miod <miod@openbsd.org> |
Split ever-growing mips <machine/cpu.h> into what 99% of the kernel needs, which will remain in <machine/cpu.h>, and a new mips_cpu.h containing only the goriest md details, which are only of interes
Split ever-growing mips <machine/cpu.h> into what 99% of the kernel needs, which will remain in <machine/cpu.h>, and a new mips_cpu.h containing only the goriest md details, which are only of interest to a handful set of files; this is similar in spirit to what alpha does, but here <machine/cpu.h> does not include the new file.
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a6ba7b46 |
| 29-Sep-2012 |
miod <miod@openbsd.org> |
Handle the coprocessor 0 cause and status registers as a 64 bit value now, as some odd mips designs need moro than 32 bits in there. This causes a lot of mechanical changes everywhere getsr() is used.
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c40b02a1 |
| 29-Sep-2012 |
miod <miod@openbsd.org> |
Proide a mips_sync() macro to wrap asm("sync"), and replace gazillions of such statements with it.
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02ec79dd |
| 17-Jun-2012 |
miod <miod@openbsd.org> |
Remove leftover loongson or sgi references.
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61e15267 |
| 08-May-2011 |
syuu <syuu@openbsd.org> |
obio renamed iobus, moved interrupt handler code to dev/octeon_intr.c
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