Mop up RC4_INDEX.

The RC4_INDEX define switches between base pointer indexing and per-byte
pointer increment. This supposedly made a huge difference to performance
on x86 at some point, however comp

Mop up RC4_INDEX.

The RC4_INDEX define switches between base pointer indexing and per-byte
pointer increment. This supposedly made a huge difference to performance
on x86 at some point, however compilers have improved somewhat since then.
There is no change (or effectively no change) in generated assembly on
a the majority of LLVM platforms and even when there is some change
(e.g. aarch64), there is no noticable performance difference.

Simplify the (still messy) macros/code and mop up RC4_INDEX.

ok tb@

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Provide a readable assembly implementation for MD5 on amd64.

This appears to be about 5% faster than the current perlasm version on a
modern Intel CPU.

While here rename md5_block_asm_data_order to

Provide a readable assembly implementation for MD5 on amd64.

This appears to be about 5% faster than the current perlasm version on a
modern Intel CPU.

While here rename md5_block_asm_data_order to md5_block_data_order, for
consistency with other hashes.

ok tb@

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Provide a SHA-1 assembly implementation for amd64 using SHA-NI.

This provides a SHA-1 assembly implementation for amd64, which uses
the Intel SHA Extensions (aka SHA New Instructions or SHA-NI). Thi

Provide a SHA-1 assembly implementation for amd64 using SHA-NI.

This provides a SHA-1 assembly implementation for amd64, which uses
the Intel SHA Extensions (aka SHA New Instructions or SHA-NI). This
provides a 2-2.5x performance gain on some Intel CPUs and many AMD CPUs.

ok tb@

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Provide a replacement assembly implementation for SHA-1 on amd64.

As already done for SHA-256 and SHA-512, replace the perlasm generated
SHA-1 assembly implementation with one that is actually reada

Provide a replacement assembly implementation for SHA-1 on amd64.

As already done for SHA-256 and SHA-512, replace the perlasm generated
SHA-1 assembly implementation with one that is actually readable. Call the
assembly implementation from a C wrapper that can, in the future, dispatch
to alternate implementations. On a modern CPU the performance is around
5% faster than the base implementation generated by sha1-x86_64.pl, however
it is around 15% slower than the excessively complex SSSE2/AVX version that
is also generated by the same script (a SHA-NI version will greatly
outperform this and is much cleaner/simpler).

ok tb@

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Provide a SHA-256 assembly implementation for amd64 using SHA-NI.

This provides a SHA-256 assembly implementation for amd64, which uses
the Intel SHA Extensions (aka SHA New Instructions or SHA-NI).

Provide a SHA-256 assembly implementation for amd64 using SHA-NI.

This provides a SHA-256 assembly implementation for amd64, which uses
the Intel SHA Extensions (aka SHA New Instructions or SHA-NI). This
provides a 3-5x performance gain on some Intel CPUs and many AMD CPUs.

ok tb@

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Provide a replacement assembly implementation for SHA-512 on amd64.

Replace the perlasm generated SHA-512 assembly with a more readable
version and the same C wrapper introduced for SHA-256. As for

Provide a replacement assembly implementation for SHA-512 on amd64.

Replace the perlasm generated SHA-512 assembly with a more readable
version and the same C wrapper introduced for SHA-256. As for SHA-256,
on a modern CPU the performance is largely the same.

ok tb@

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Add CPU capability detection for the Intel SHA extensions (aka SHA-NI).

This also provides a crypto_cpu_caps_amd64 variable that can be checked
for CRYPTO_CPU_CAPS_AMD64_SHA.

ok tb@

Add comment for crypto_cpu_caps_aarch64.

Check the correct variable in cpuid().

Provide a replacement assembly implementation for SHA-256 on amd64.

Replace the perlasm generated SHA-256 assembly implementation with one that
is actually readable. Call the assembly implementation

Provide a replacement assembly implementation for SHA-256 on amd64.

Replace the perlasm generated SHA-256 assembly implementation with one that
is actually readable. Call the assembly implementation from a C wrapper
that can, in the future, dispatch to alternate implementations. Performance
is similar (or even better) on modern CPUs, while somewhat slower on older
CPUs (this is in part due to the wrapper, the impact of which is more
noticable with small block sizes).

Thanks to gkoehler@ and tb@ for testing.

ok tb@

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Replace aarch64 CPU capabilities detection code.

Replace the aarch64 CPU detection code with a version that parses ISAR0,
avoiding signal handling and SIGILL. This gets ISAR0 via sysctl(), but this

Replace aarch64 CPU capabilities detection code.

Replace the aarch64 CPU detection code with a version that parses ISAR0,
avoiding signal handling and SIGILL. This gets ISAR0 via sysctl(), but this
can be adapted to other mechanisms for other platforms (or alternatively
the same can be achieved via HWCAP).

This now follows the same naming/design as used by amd64 and i386, hence
define HAVE_CRYPTO_CPU_CAPS_INIT for aarch64.

ok kettenis@ tb@

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cryptlib.h: adjust header guard for upcoming surgery

It is gross that an internal detail leaked into a public header, but,
hey, it's openssl. No hack is too terrible to appear in this library.
opens

cryptlib.h: adjust header guard for upcoming surgery

It is gross that an internal detail leaked into a public header, but,
hey, it's openssl. No hack is too terrible to appear in this library.
opensslconf.h needs major pruning but the day that happens is not today.

ok jsing

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Clean up PPC CPU capabilities and Montgomery code.

ppc64-mont.pl (which produces bn_mul_mont_fpu64()) is unused on both
powerpc and powerpc64, so remove it. ppccap.c doesn't actually contain
anythin

Clean up PPC CPU capabilities and Montgomery code.

ppc64-mont.pl (which produces bn_mul_mont_fpu64()) is unused on both
powerpc and powerpc64, so remove it. ppccap.c doesn't actually contain
anything to do with CPU capabilities - it just provides a bn_mul_mont()
that calls bn_mul_mont_int() (which ppc-mont.pl generates). Change
ppc-mont.pl to generate bn_mul_mont() directly and remove ppccap.c.

ok tb@

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Remove IA32 specific code from cryptlib.c.

Move the IA32 specific code to arch/{amd64,i386}/crypto_cpu_caps.c, rather
than polluting cryptlib.c with machine dependent code. A stub version of
crypto_

Remove IA32 specific code from cryptlib.c.

Move the IA32 specific code to arch/{amd64,i386}/crypto_cpu_caps.c, rather
than polluting cryptlib.c with machine dependent code. A stub version of
crypto_cpu_caps_ia32() still remains for now.

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Remove unused sparc CPU capability detection code.

This has been unused for a long time - it can be found in the attic if
someone wants to clean it up and enable it in the future.

ok tb@

Provide crypto_cpu_caps_init() for i386.

This is the same CPU capabilities code that is now used for amd64. Like
amd64 we now only populate OPENSSL_ia32cap_P with bits used by perlasm.

Discussed wi

Provide crypto_cpu_caps_init() for i386.

This is the same CPU capabilities code that is now used for amd64. Like
amd64 we now only populate OPENSSL_ia32cap_P with bits used by perlasm.

Discussed with tb@

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Provide crypto_cpu_caps_init() for amd64.

This is a CPU capability detection implementation in C, with minimal
inline assembly (for cpuid and xgetbv). This replaces the assembly
mess generated by x8

Provide crypto_cpu_caps_init() for amd64.

This is a CPU capability detection implementation in C, with minimal
inline assembly (for cpuid and xgetbv). This replaces the assembly
mess generated by x86_64cpuid.pl. Rather than populating OPENSSL_ia32cap_P
directly with CPUID output, just set the bits that the remaining
perlasm checks (namely AESNI, AVX, FXSR, INTEL, HT, MMX, PCLMUL, SSE, SSE2
and SSSE3).

ok joshua@ tb@

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Unexport OPENSSL_cpuid_setup and OPENSSL_ia32cap_P

This allows us in particular to get rid of the MD Symbols.list which
were needed on amd64 and i386 for llvm 16 a while back. OPENSSL_ia32cap_P
was

Unexport OPENSSL_cpuid_setup and OPENSSL_ia32cap_P

This allows us in particular to get rid of the MD Symbols.list which
were needed on amd64 and i386 for llvm 16 a while back. OPENSSL_ia32cap_P
was never properly exported since the symbols were marked .hidden in the
asm.

ok beck jsing

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repair bizzare indents; ok tb