| #
db06c1e0 |
| 07-Jul-2023 |
msaitoh <msaitoh@NetBSD.org> |
tprof(8): Add support for Skylake-X and Cascade Lake.
|
| #
06806094 |
| 07-Jul-2023 |
msaitoh <msaitoh@NetBSD.org> |
Modify comment. No functional change.
|
| #
e2b25c5d |
| 12-Apr-2023 |
msaitoh <msaitoh@NetBSD.org> |
KNF. No functional change.
|
| #
e1e63153 |
| 10-Apr-2023 |
msaitoh <msaitoh@NetBSD.org> |
Add Cometlake support.
|
| #
db24b2c2 |
| 08-Dec-2022 |
msaitoh <msaitoh@NetBSD.org> |
Add AMD family 19h (zen3 and zen4) support to tprof.
|
| #
f1f580f5 |
| 08-Dec-2022 |
msaitoh <msaitoh@NetBSD.org> |
Use lowercase consistently for hexadecimal numbers. No functional change.
|
| #
f5823b20 |
| 07-Dec-2022 |
msaitoh <msaitoh@NetBSD.org> |
KNF. No functional change.
|
| #
052df59b |
| 13-Jun-2022 |
msaitoh <msaitoh@NetBSD.org> |
Disable the unsupported events from the bit vector length in EAX.
|
| #
c07439c6 |
| 13-Jun-2022 |
msaitoh <msaitoh@NetBSD.org> |
Add topdown-slots to Intel architectural performance monitoring version 1.
|
| #
0a27bcec |
| 17-Apr-2020 |
knakahara <knakahara@NetBSD.org> |
Fix typo in a comment.
|
| #
1434425d |
| 11-Oct-2019 |
jmcneill <jmcneill@NetBSD.org> |
Add support for AMD Family 15h
|
| #
0acc4e3e |
| 29-May-2019 |
maxv <maxv@NetBSD.org> |
Add support for AMD Family 17h.
|
| #
4ed6c77e |
| 26-Nov-2018 |
knakahara <knakahara@NetBSD.org> |
tprof: Add goldmont plus support. Tested by msaitoh@n.o, thanks.
|
| #
4fd01caa |
| 26-Nov-2018 |
knakahara <knakahara@NetBSD.org> |
tprof: Add goldmont support.
I tested on Atom C3558 (Denverton).
|
| #
a8700cbe |
| 15-Nov-2018 |
knakahara <knakahara@NetBSD.org> |
tprof: Add silvermont, airmont support.
I tested on Atom C2758 (Rangeley).
|
| #
9896bc73 |
| 14-Jul-2018 |
maxv <maxv@NetBSD.org> |
Finish the Skylake/Kabylake table, and improve the output of "tprof analyze".
|
| #
48aa8146 |
| 13-Jul-2018 |
maxv <maxv@NetBSD.org> |
Skylake/Kabylake are family 6, so add a check for that. While here improve
the layout of "tprof list".
|
| #
8dd2f31a |
| 13-Jul-2018 |
maxv <maxv@NetBSD.org> |
Inline the values in amd_f10h_names[], we're not going to use defines for
each CPU model found in the wild.
|
| #
a087cb3c |
| 13-Jul-2018 |
maxv <maxv@NetBSD.org> |
Revamp tprof.
Rewrite the Intel backend to use the generic PMC interface, which is
available on all Intel CPUs. Synchronize the AMD backend with the new
interface.
The kernel identifies the PMC int
Revamp tprof.
Rewrite the Intel backend to use the generic PMC interface, which is
available on all Intel CPUs. Synchronize the AMD backend with the new
interface.
The kernel identifies the PMC interface, and gives its id to userland.
Userland then queries the events itself (via cpuid etc). These events
depend on the PMC interface.
The tprof utility is rewritten to allow the user to choose which event
to count (which was not possible until now, the event was hardcoded in
the backend). The command line format is based on usr.bin/pmc, eg:
tprof -e llc-misses:k -o output sleep 20
The man page is updated too, but the arguments will likely change soon
anyway so it doesn't matter a lot.
The tprof utility has three tables:
Intel Architectural Version 1
Intel Skylake/Kabylake
AMD Family 10h
A CPU can support a combination of tables. For example Kabylake has
Intel-Architectural-Version-1 and its own Intel-Kabylake table.
For now the Intel Skylake/Kabylake table contains only one event, just
to demonstrate that the combination of tables works. Tested on an
Intel Core i5 Kabylake.
The code for AMD Family 10h is taken from the code I had written for
usr.bin/pmc. I haven't tested it yet, but it's the same as pmc(1), so
I guess it works as-is.
The whole thing is written in such a way that (I think) it is not
complicated to add more CPU models, and more architectures (other than
x86).
show more ...
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