Add tests for AVX-512 registers (zmm0..zmm31, k0..7)

Thanks to David Seifert <soap@gentoo.org> for providing a VM
on an AVX-512 capable hardware

Reviewed by kamil

Issue 64-bit versions of *XSAVE* for 64-bit amd64 programs

When calling FXSAVE, XSAVE, FXRSTOR, ... for 64-bit programs on amd64
use the 64-suffixed variant in order to include the complete FIP/FDP

Issue 64-bit versions of *XSAVE* for 64-bit amd64 programs

When calling FXSAVE, XSAVE, FXRSTOR, ... for 64-bit programs on amd64
use the 64-suffixed variant in order to include the complete FIP/FDP
registers in the x87 area.

The difference between the two variants is that the FXSAVE64 (new)
variant represents FIP/FDP as 64-bit fields (union fp_addr.fa_64),
while the legacy FXSAVE variant uses split fields: 32-bit offset,
16-bit segment and 16-bit reserved field (union fp_addr.fa_32).
The latter implies that the actual addresses are truncated to 32 bits
which is insufficient in modern programs.

The change is applied only to 64-bit programs on amd64. Plain i386
and compat32 continue using plain FXSAVE. Similarly, NVMM is not
changed as I am not familiar with that code.

This is a potentially breaking change. However, I don't think it likely
to actually break anything because the data provided by the old variant
were not meaningful (because of the truncated pointer).

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Remove leftover commented out #if 0

Fix s87_tw reconstruction to correctly indicate register states

Fix the code reconstructing s87_tw (full tag word) from fx_sw (abridged
tag word) to correctly represent all register states. The pre

Fix s87_tw reconstruction to correctly indicate register states

Fix the code reconstructing s87_tw (full tag word) from fx_sw (abridged
tag word) to correctly represent all register states. The previous code
only distinguished between empty/non-empty registers, and assigned
'regular value' to all non-empty registers. The new code explicitly
distinguishes the two other tag word values: empty and special.

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Add tests for x87 FPU registers

Reviewed by kamil

Rename MM_REG macro to ST_MAN, and cover fpr/xstate with it

Rename the MM_REG macro to ST_MAN, to make it clearer that it gets
mantissa of ST registers which overlaps with MM registers but can be
al

Rename MM_REG macro to ST_MAN, and cover fpr/xstate with it

Rename the MM_REG macro to ST_MAN, to make it clearer that it gets
mantissa of ST registers which overlaps with MM registers but can be
also used to read ST registers (to be used in the next commit). Extend
it to cover the difference between GETFPREGS and GETXSTATE,
and therefore avoid additional condition on i386.

Reviewed by kamil.

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Update for new LWP behavior -- as of 9.99.59, the LWP ID of a single-LWP
process is the PID, not 1.

Refactor dbregs_dont_inherit_lwp()

Switch from native LWP calls to pthread(3) calls.

Instead of turning optimization off, use unique labels with %= (thanks joerg@)

adjust r1.19; add clang equivalent of gcc specific attribute

Extend concurrent events test to watchpoints

Extend concurrent events test to breakpoints

Add testing for concurrent breakpoint hits. The code is currently
x86-specific but since it reuses most of the generic concurrent event
test code, it's

Extend concurrent events test to breakpoints

Add testing for concurrent breakpoint hits. The code is currently
x86-specific but since it reuses most of the generic concurrent event
test code, it's put in t_ptrace_wait.c with arch-specific hooks.

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Turn off optimization on a function which contains constant labels.
The optimizer splits it and we end up with 2 copies and duplicate symbols.

Add tests for reading registers from x86 core dumps

Combine x86 register tests into unified test function

Reduce the code duplication and improve maintainability of x86 register
tests by combining all of them to a single base function.

Implement PT_GETXSTATE and PT_SETXSTATE

Introduce two new ptrace() requests: PT_GETXSTATE and PT_SETXSTATE,
that provide access to the extended (and extensible) set of FPU
registers on amd64 and i38

Implement PT_GETXSTATE and PT_SETXSTATE

Introduce two new ptrace() requests: PT_GETXSTATE and PT_SETXSTATE,
that provide access to the extended (and extensible) set of FPU
registers on amd64 and i386. At the moment, this covers AVX (YMM)
and AVX-512 (ZMM, opmask) registers. It can be easily extended
to cover further register types without breaking backwards
compatibility.

PT_GETXSTATE issues the XSAVE instruction with all kernel-supported
extended components enabled. The data is copied into 'struct xstate'
(which -- unlike the XSAVE area itself -- has stable format
and offsets).

PT_SETXSTATE issues the XRSTOR instruction to restore the register
values from user-provided 'struct xstate'. The function replaces only
the specific XSAVE components that are listed in 'xs_rfbm' field,
making it possible to issue partial updates.

Both syscalls take a 'struct iovec' pointer rather than a direct
argument. This requires the caller to explicitly specify the buffer
size. As a result, existing code will continue to work correctly
when the structure is extended (performing partial reads/updates).

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Fix alignment of SSE filling data

Add more debug to register writing tests

Add PT_SET*REGS tests for mm/xmm registers.

Remove obsolete size asserts.

Use newly-filled i386 reg structs in PT_GETFPREGS & PT_GETXMMREGS tests.

Add ptrace() tests for reading mm* and xmm* registers

Link t_ptrace_wait* tests with -pthread

While there, bump (c) for ATF ptrace(2) tests.

Add __used in infinite_thread() for consistency with other functions in
the file.

Add missing break keywords in t_ptrace_wait* x86 tests

Add missing break in switch() cases in dbregs_trap_variable().

Reported by <mrg>
Detected by GCC 7

Port the CVE 2018-8897 mitigation to i386 ATF ptrace(2) tests

On i386 there is no need to switch execution mode.
Use 0x23 SS selector for i386, amd64 used 0x4f.

Based on pointers from <maxv>.

Spon

Port the CVE 2018-8897 mitigation to i386 ATF ptrace(2) tests

On i386 there is no need to switch execution mode.
Use 0x23 SS selector for i386, amd64 used 0x4f.

Based on pointers from <maxv>.

Sponsored by <The NetBSD Foundation>

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