History log of /netbsd-src/sys/arch/mips/include/cache_octeon.h (Results 1 – 5 of 5)
Revision Date Author Comments
# 1b968d3c 26-Jul-2020 simonb <simonb@NetBSD.org>

#define<tab>
Nuke trailing whitespace.


# 8101407b 14-Jun-2020 simonb <simonb@NetBSD.org>

Define Octeon Cavium cache layouts for various cnMIPS cores.


# 991dc94f 11-Apr-2019 simonb <simonb@NetBSD.org>

Fix tyop.


# d7e78fcf 11-Jul-2016 matt <matt@NetBSD.org>

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch


# f693c922 29-Apr-2015 hikaru <hikaru@NetBSD.org>

Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet In

Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.

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