riscv: Make feraiseexcept actually raise the given exceptions.

Doing

fexcept_t ex = 0;
fesetexceptflag(&ex, excepts);

has the effect of _clearing_ all the exceptions in excepts. Using
fesetexce

riscv: Make feraiseexcept actually raise the given exceptions.

Doing

fexcept_t ex = 0;
fesetexceptflag(&ex, excepts);

has the effect of _clearing_ all the exceptions in excepts. Using
fesetexceptflag doesn't make this easier, because we would have to
record which exceptions were already raised. So just set the fflags
bits in the fcsr register directly.

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RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

fix typos in comments, mainly s/extention/extension/ and s/sufficent/sufficient/

provide a common softfloat fenv implemenation and use it for softfloat builds.
restore ABI compatibility with previous releases for ieeefp.h on sh3.
add namespace.h protection for all the fenv interf

provide a common softfloat fenv implemenation and use it for softfloat builds.
restore ABI compatibility with previous releases for ieeefp.h on sh3.
add namespace.h protection for all the fenv interfaces.
use MKSOFTFLOAT on sh3 instead of assuming softfloat.
standardize on comparing MKSOFTFLOAT with "no".
remove the arm-specific softfloat fenv code (which also had several bugs).
fix logic errors in the arm hardfloat feraiseexcept() and feupdateenv().

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New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)