Revision tags: llvmorg-21-init |
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#
ef4800c9 |
| 15-Jan-2025 |
Diego Caballero <dieg0ca6aller0@gmail.com> |
[mlir][Interfaces][NFC] Update doc of ViewLikeOpInterface parser/printer handlers (#122555)
This PR addresses part of the feedback provided in #115808.
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Revision tags: llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6 |
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#
2c1c6767 |
| 08-May-2024 |
srcarroll <50210727+srcarroll@users.noreply.github.com> |
[mlir][transform] Consistent `linalg` `transform` op syntax for dynamic index lists (#90897)
This patch is a first pass at making consistent syntax across the
`LinalgTransformOp`s that use dynamic
[mlir][transform] Consistent `linalg` `transform` op syntax for dynamic index lists (#90897)
This patch is a first pass at making consistent syntax across the
`LinalgTransformOp`s that use dynamic index lists for size parameters.
Previously, there were two different forms: inline types in the list, or
place them in the functional style tuple. This patch goes for the
latter.
In order to do this, the `printPackedOrDynamicIndexList`,
`printDynamicIndexList` and their `parse` counterparts were modified so
that the types can be optionally provided to the corresponding custom
directives.
All affected ops now use tablegen `assemblyFormat`, so custom
`parse`/`print` functions have been removed. There are a couple ops that
will likely add dynamic size support, and once that happens it should be
made sure that the assembly remains consistent with the changes in this
patch.
The affected ops are as follows: `pack`, `pack_greedily`,
`tile_using_forall`. The `tile_using_for` and `vectorize` ops already
used this syntax, but their custom assembly was removed.
---------
Co-authored-by: Oleksandr "Alex" Zinenko <ftynse@gmail.com>
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Revision tags: llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2 |
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#
e0b19e95 |
| 18-Mar-2024 |
Mehdi Amini <joker.eph@gmail.com> |
[MLIR] Remove unused implicit capture in the lambda (NFC)
This lambda does not capture anything, the `&` is just misleading.
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Revision tags: llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6 |
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#
1949fe90 |
| 16-Nov-2023 |
Rik Huijzer <github@huijzer.xyz> |
[mlir] Verify non-negative `offset` and `size` (#72059)
In #71153, the `memref.subview` canonicalizer crashes due to a negative
`size` being passed as an operand. During `SubViewOp::verify` this
n
[mlir] Verify non-negative `offset` and `size` (#72059)
In #71153, the `memref.subview` canonicalizer crashes due to a negative
`size` being passed as an operand. During `SubViewOp::verify` this
negative `size` is not yet detectable since it is dynamic and only
available after constant folding, which happens during the
canonicalization passes. As discussed in
<https://discourse.llvm.org/t/rfc-more-opfoldresult-and-mixed-indices-in-ops-that-deal-with-shaped-values/72510>,
the verifier should not be extended as it should "only verify local
aspects of an operation".
This patch fixes #71153 by not folding in aforementioned situation.
Also, this patch adds a basic offset and size check in the
`OffsetSizeAndStrideOpInterface` verifier.
Note: only `offset` and `size` are checked because `stride` is allowed
to be negative
(https://github.com/llvm/llvm-project/commit/54d81e49e3b72f6a305891fe169ecd7c6f559223).
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Revision tags: llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2 |
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#
b2d1de2d |
| 03-Aug-2023 |
Matthias Springer <me@m-sp.org> |
[mlir][Interfaces][NFC] Delete dead code from OffsetSizeAndStrideOpInterface
Also make `getNumDynamicEntriesUpToIdx` a helper function. It does not have to be an interface method.
Differential Revi
[mlir][Interfaces][NFC] Delete dead code from OffsetSizeAndStrideOpInterface
Also make `getNumDynamicEntriesUpToIdx` a helper function. It does not have to be an interface method.
Differential Revision: https://reviews.llvm.org/D156864
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#
a1f04b70 |
| 03-Aug-2023 |
Matthias Springer <me@m-sp.org> |
[mlir][Interfaces][NFC] Use camel case for offset/size/stride accessors
This is for consistency with the remaining MLIR code base.
Differential Revision: https://reviews.llvm.org/D156857
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Revision tags: llvmorg-17.0.0-rc1, llvmorg-18-init |
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#
c73053c2 |
| 05-Jul-2023 |
Benjamin Kramer <benny.kra@googlemail.com> |
Make python into C++
`not` is a C++ keyword, but it seems to cause trouble with MSVC
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#
ad7ef192 |
| 02-Jul-2023 |
Andrzej Warzynski <andrzej.warzynski@arm.com> |
[mlir][transform] Allow arbitrary indices to be scalable
This change lifts the limitation that only the trailing dimensions/sizes in dynamic index lists can be scalable. It allows us to extend `Mask
[mlir][transform] Allow arbitrary indices to be scalable
This change lifts the limitation that only the trailing dimensions/sizes in dynamic index lists can be scalable. It allows us to extend `MaskedVectorizeOp` and `TileOp` from the Transform dialect so that the following is allowed:
%1, %loops:3 = transform.structured.tile %0 [4, [4], [4]]
This is also a follow up for https://reviews.llvm.org/D153372 that will enable the following (middle vector dimension is scalable):
transform.structured.masked_vectorize %0 vector_sizes [2, [4], 8]
To facilate this change, the hooks for parsing and printing dynamic index lists are updated accordingly (`printDynamicIndexList` and `parseDynamicIndexList`, respectively). `MaskedVectorizeOp` and `TileOp` are updated to include an array of attribute of bools that captures whether the corresponding vector dimension/tile size, respectively, are scalable or not.
NOTE 1: I am re-landing this after the initial version was reverted. To fix the regression and in addition to the original patch, this revision updates the Python bindings for the transform dialect
NOTE 2: This change is a part of a larger effort to enable scalable vectorisation in Linalg. See this RFC for more context: * https://discourse.llvm.org/t/rfc-scalable-vectorisation-in-linalg/
This relands 048764f23a380fd6f8cc562a0008dcc6095fb594 with fixes.
Differential Revision: https://reviews.llvm.org/D154336
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#
14d073b5 |
| 04-Jul-2023 |
Alexander Belyaev <pifon@google.com> |
Revert "[mlir][transform] Allow arbitrary indices to be scalable"
This reverts commit 048764f23a380fd6f8cc562a0008dcc6095fb594.
Breaks https://lab.llvm.org/buildbot/#/builders/61/builds/45451
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#
048764f2 |
| 02-Jul-2023 |
Andrzej Warzynski <andrzej.warzynski@arm.com> |
[mlir][transform] Allow arbitrary indices to be scalable
This change lifts the limitation that only the trailing dimensions/sizes in dynamic index lists can be scalable. It allows us to extend `Mask
[mlir][transform] Allow arbitrary indices to be scalable
This change lifts the limitation that only the trailing dimensions/sizes in dynamic index lists can be scalable. It allows us to extend `MaskedVectorizeOp` and `TileOp` from the Transform dialect so that the following is allowed:
%1, %loops:3 = transform.structured.tile %0 [[4], [4], 4]
This is also a follow up for https://reviews.llvm.org/D153372 that will enable the following (middle vector dimension is scalable):
transform.structured.masked_vectorize %0 vector_sizes [2, [4], 8]
To facilate this change, the hooks for parsing and printing dynamic index lists are updated accordingly (`printDynamicIndexList` and `parseDynamicIndexList`, respectively). `MaskedVectorizeOp` and `TileOp` are updated to include an array of attribute of bools that captures whether the corresponding vector dimension/tile size, respectively, are scalable or not.
This change is a part of a larger effort to enable scalable vectorisation in Linalg. See this RFC for more context: * https://discourse.llvm.org/t/rfc-scalable-vectorisation-in-linalg/
Differential Revision: https://reviews.llvm.org/D154336
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Revision tags: llvmorg-16.0.6, llvmorg-16.0.5 |
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#
7a52f791 |
| 01-Jun-2023 |
Andrzej Warzynski <andrzej.warzynski@arm.com> |
[mlir][transform] Add support for expressing scalable vector sizes
This patch enables specifying scalable vector sizes when using the Transform dialect to drive vectorisation, e.g.: ``` transform.st
[mlir][transform] Add support for expressing scalable vector sizes
This patch enables specifying scalable vector sizes when using the Transform dialect to drive vectorisation, e.g.: ``` transform.structured.masked_vectorize %0 vector_sizes [8, 16, [4]] ``` This is implemented by extending the MaskedVectorizeOp with a dedicated attribute for "scalability" and by overloading `parseDynamicIndexList` so that MaskedVectorizeOp can continue using the auto-generated parser and printer.
At the moment, only the trailing vec size can be scalable. The following is not yet supported: ``` transform.structured.masked_vectorize %0 vector_sizes [8, [16], [4]] ```
As the vectoriser does not support scalable vectorisation just yet, a warning is issues when scalable vector sizes are used. You can also use the debug output, `--debug-only=linalg-vectorization`, to check whether scalable vectorisation has been switched on.
This change is a part of a larger effort to enable scalable vectorisation in Linalg. See this RFC for more context: * https://discourse.llvm.org/t/rfc-scalable-vectorisation-in-linalg/ Similar patch for tiling: https://reviews.llvm.org/D150944
Differential Revision: https://reviews.llvm.org/D151892
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#
726835cd |
| 01-Jun-2023 |
Andrzej Warzynski <andrzej.warzynski@arm.com> |
[mlir] Update how scalable indices are printed
This patch makes sure that scalable indices (that would normally represent scalable tile or vector sizes) are printed correctly, i.e. with additional s
[mlir] Update how scalable indices are printed
This patch makes sure that scalable indices (that would normally represent scalable tile or vector sizes) are printed correctly, i.e. with additional square brackets: ``` %1, %loop = transform.structured.tile %0 [2, 8, [4]] ```
This change complements https://reviews.llvm.org/D150944 and is a part of a larger effort to enable scalable vectorisation in Linalg. See this RFC for more context: * https://discourse.llvm.org/t/rfc-scalable-vectorisation-in-linalg/
Differential Revision: https://reviews.llvm.org/D151978
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Revision tags: llvmorg-16.0.4 |
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#
a5b3677d |
| 16-May-2023 |
Andrzej Warzynski <andrzej.warzynski@arm.com> |
[mlir][transform] Add support for expressing scalable tile sizes
This patch enables specifying scalable tile sizes when using the Transform dialect to drive tiling, e.g.: ``` %1, %loop = transform.s
[mlir][transform] Add support for expressing scalable tile sizes
This patch enables specifying scalable tile sizes when using the Transform dialect to drive tiling, e.g.: ``` %1, %loop = transform.structured.tile %0 [[4]] ``` This is implemented by extending the TileOp with a dedicated attribute for "scalability" and by updating various parsing hooks. At the moment, only the trailing tile size can be scalable. The following is not yet supported: ``` %1, %loop = transform.structured.tile %0 [[4], [4]] ```
This change is a part of larger effort to enable scalable vectorisation in Linalg. See this RFC for more context: * https://discourse.llvm.org/t/rfc-scalable-vectorisation-in-linalg/
Differential Revision: https://reviews.llvm.org/D150944
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Revision tags: llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3 |
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#
2fe4d90c |
| 21-Feb-2023 |
Alex Zinenko <zinenko@google.com> |
[mlir] make structured transform ops use types
Types have been introduced a while ago and provide for better readability and transform-time verification. Use them in the ops from the structured tran
[mlir] make structured transform ops use types
Types have been introduced a while ago and provide for better readability and transform-time verification. Use them in the ops from the structured transform dialect extension.
In most cases, the types are appended as trailing functional types or a derived format of the functional type that allows for an empty right hand size without the annoying `-> ()` syntax (similarly to `func.func` declaration that may omit the arrow). When handles are used inside mixed static/dynamic lists, such as tile sizes, types of those handles follow them immediately as in `sizes [%0 : !transform.any_value, 42]`. This allows for better readability than matching the trailing type.
Update code to remove hardcoded PDL dependencies and expunge PDL from structured transform op code.
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D144515
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#
310deca2 |
| 17-Feb-2023 |
Alexander Belyaev <pifon@google.com> |
[mlir] Add loop bounds to scf.foreach_thread.
https://discourse.llvm.org/t/rfc-parallel-loops-on-tensors-in-mlir/68332
Differential Revision: https://reviews.llvm.org/D144072
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Revision tags: llvmorg-16.0.0-rc2 |
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#
ee308c99 |
| 02-Feb-2023 |
Jacques Pienaar <jpienaar@google.com> |
[mlir][py] Fix infer return type invocation for variadics
Previously we only allowed the flattened list passed in, but the same input provided here as to buildGeneric so flatten accordingly. We have
[mlir][py] Fix infer return type invocation for variadics
Previously we only allowed the flattened list passed in, but the same input provided here as to buildGeneric so flatten accordingly. We have less info here than in buildGeneric so the error is more generic if unpacking fails.
Differential Revision: https://reviews.llvm.org/D143240
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Revision tags: llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6 |
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#
baca3b38 |
| 25-Nov-2022 |
Lorenzo Chelini <l.chelini@icloud.com> |
[MLIR] Simplify logic in `parseDynamicIndexList` (NFC)
We can use `parseCommaSeparatedList` to simplify the logic of `parseDynamicIndexList`. We don't need to explicitly check delimiters and comma a
[MLIR] Simplify logic in `parseDynamicIndexList` (NFC)
We can use `parseCommaSeparatedList` to simplify the logic of `parseDynamicIndexList`. We don't need to explicitly check delimiters and comma anymore, this is done for us by `parseCommaSeparatedList`.
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D138694
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#
a9733b8a |
| 22-Nov-2022 |
Lorenzo Chelini <l.chelini@icloud.com> |
[MLIR] Adopt `DenseI64ArrayAttr` in tensor, memref and linalg transform
This commit is a first step toward removing inconsistencies between dynamic and static attributes (i64 v. index) by dropping `
[MLIR] Adopt `DenseI64ArrayAttr` in tensor, memref and linalg transform
This commit is a first step toward removing inconsistencies between dynamic and static attributes (i64 v. index) by dropping `I64ArrayAttr` and using `DenseI64ArrayAttr` in Tensor, Memref and Linalg Transform ops. In Linalg Transform ops only `TileToScfForOp` and `TileOp` have been updated.
See related discussion: https://discourse.llvm.org/t/rfc-inconsistency-between-dynamic-and-static-attributes-i64-v-index/66612/1
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D138567
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#
65b72a78 |
| 22-Nov-2022 |
Alexander Belyaev <pifon@google.com> |
[mlir] Clean-up ViewLikeOpInterface w.r.t. kDynamic change.
Differential Revision: https://reviews.llvm.org/D138478
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#
399638f9 |
| 18-Nov-2022 |
Aliia Khasanova <aliia@google.com> |
Merge kDynamicSize and kDynamicSentinel into one constant.
resolve conflicts
Differential Revision: https://reviews.llvm.org/D138282
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Revision tags: llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0 |
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#
0b1aee38 |
| 02-Sep-2022 |
Mehdi Amini <joker.eph@gmail.com> |
Revert "[mlir][Tensor] Add rewrites to extract slices through `tensor.collape_shape`"
This reverts commit 5711957875738c1318f89afd7bf4be388f85a087.
A circular dependency is introduced here from Dia
Revert "[mlir][Tensor] Add rewrites to extract slices through `tensor.collape_shape`"
This reverts commit 5711957875738c1318f89afd7bf4be388f85a087.
A circular dependency is introduced here from Dialect/Utils/ to the ViewLikeInterface, but it already depends on Dialect/Utils.
Also this introduces a dependency from lib/Dialect/Tensor to Linalg, which isn't obviously correct from a layering point of view.
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Revision tags: llvmorg-15.0.0-rc3 |
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#
57119578 |
| 16-Aug-2022 |
Christopher Bate <cbate@nvidia.com> |
[mlir][Tensor] Add rewrites to extract slices through `tensor.collape_shape`
This change adds a set of utilities to replace the result of a `tensor.collapse_shape -> tensor.extract_slice` chain with
[mlir][Tensor] Add rewrites to extract slices through `tensor.collape_shape`
This change adds a set of utilities to replace the result of a `tensor.collapse_shape -> tensor.extract_slice` chain with the equivalent result formed by aggregating slices of the `tensor.collapse_shape` source. In general, it is not possible to commute `extract_slice` and `collapse_shape` if linearized dimensions are sliced. The i-th dimension of the `tensor.collapse_shape` result is a "linearized sliced dimension" if:
1) Reassociation indices of tensor.collapse_shape in the i'th position is greater than size 1 (multiple dimensions of the input are collapsed) 2) The i-th dimension is sliced by `tensor.extract_slice`.
We can work around this by stitching together the result of `tensor.extract_slice` by iterating over any linearized sliced dimensions. This is equivalent to "tiling" the linearized-and-sliced dimensions of the `tensor.collapse_shape` operation in order to manifest the result tile (the result of the `tensor.extract_slice`). The user of the utilities must provide the mechanism to create the tiling (e.g. a loop). In the tests, it is demonstrated how to apply the utilities using either `scf.for` or `scf.foreach_thread`.
The below example illustrates the pattern using `scf.for`:
``` %0 = linalg.generic ... -> tensor<3x7x11x10xf32> %1 = tensor.collapse_shape %0 [[0, 1, 2], [3]] : ... to tensor<341x10xf32> %2 = tensor.extract_slice %1 [13, 0] [10, 10] [2, 1] : .... tensor<10x10xf32> ```
We can construct %2 by generating the following IR:
``` %dest = linalg.init_tensor() : tensor<10x10xf32> %2 = scf.for %iv = %c0 to %c10 step %c1 iter_args(%arg0) -> tensor<10x10xf32> { // Step 1: Map this output idx (%iv) to a multi-index for the input (%3): %linear_index = affine.apply affine_map<(d0)[]->(d0*2 + 11)>(%iv) %3:3 = arith.delinearize_index %iv into (3, 7, 11) // Step 2: Extract the slice from the input %4 = tensor.extract_slice %0 [%3#0, %3#1, %3#2, 0] [1, 1, 1, 10] [1, 1, 1, 1] : tensor<3x7x11x10xf32> to tensor<1x1x1x10xf32> %5 = tensor.collapse_shape %4 [[0, 1, 2], [3]] : tensor<1x1x1x10xf32> into tensor<1x10xf32> // Step 3: Insert the slice into the destination %6 = tensor.insert_slice %5 into %arg0 [%iv, 0] [1, 10] [1, 1] : tensor<1x10xf32> into tensor<10x10xf32> scf.yield %6 : tensor<10x10xf32> } ```
The pattern was discussed in the RFC here: https://discourse.llvm.org/t/rfc-tensor-extracting-slices-from-tensor-collapse-shape/64034
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D129699
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#
a2ad3ec7 |
| 10-Aug-2022 |
Jeff Niu <jeff@modular.com> |
[mlir][ods] Support string literals in `custom` directives
This patch adds support for string literals as `custom` directive arguments. This can be useful for re-using custom parsers and printers wh
[mlir][ods] Support string literals in `custom` directives
This patch adds support for string literals as `custom` directive arguments. This can be useful for re-using custom parsers and printers when arguments have a known value. For example:
``` ParseResult parseTypedAttr(AsmParser &parser, Attribute &attr, Type type) { return parser.parseAttribute(attr, type); }
void printTypedAttr(AsmPrinter &printer, Attribute attr, Type type) { return parser.printAttributeWithoutType(attr); } ```
And in TableGen:
``` def FooOp : ... { let arguments = (ins AnyAttr:$a); let assemblyFormat = [{ custom<TypedAttr>($a, "$_builder.getI1Type()") attr-dict }]; }
def BarOp : ... { let arguments = (ins AnyAttr:$a); let assemblyFormat = [{ custom<TypedAttr>($a, "$_builder.getIndexType()") attr-dict }]; } ```
Instead of writing two separate sets of custom parsers and printers.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D131603
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Revision tags: llvmorg-15.0.0-rc2 |
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#
c8e6ebd7 |
| 06-Aug-2022 |
Kazu Hirata <kazu@google.com> |
Use value instead of getValue (NFC)
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#
9750648c |
| 06-Aug-2022 |
Kazu Hirata <kazu@google.com> |
[mlir, flang] Use has_value instead of hasValue (NFC)
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