Revision tags: llvmorg-21-init |
|
#
4e8c9d28 |
| 16-Jan-2025 |
Jay Foad <jay.foad@amd.com> |
[TableGen] Use std::pair instead of std::make_pair. NFC. (#123174)
Also use brace initialization and emplace to avoid explicitly
constructing std::pair, and the same for std::tuple.
|
#
618ac908 |
| 15-Jan-2025 |
Kazu Hirata <kazu@google.com> |
[TableGen] Avoid repeated hash lookups (NFC) (#123018)
|
Revision tags: llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3 |
|
#
00ca2071 |
| 29-Oct-2024 |
Jerry Sun <105613447+jerryyiransun@users.noreply.github.com> |
[TableGen] [NFC] Remove unused includes in TableGen BE (#113725)
split PR as requested from
https://github.com/llvm/llvm-project/pull/113318.
Removes unused imports in TableGen BE
|
#
62e2c7fb |
| 18-Oct-2024 |
Rahul Joshi <rjoshi@nvidia.com> |
[LLVM][TableGen] Change all `Init` pointers to const (#112705)
This is a part of effort to have better const correctness in TableGen
backends:
https://discourse.llvm.org/t/psa-planned-changes-
[LLVM][TableGen] Change all `Init` pointers to const (#112705)
This is a part of effort to have better const correctness in TableGen
backends:
https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
show more ...
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Revision tags: llvmorg-19.1.2 |
|
#
d883ef10 |
| 04-Oct-2024 |
Rahul Joshi <rjoshi@nvidia.com> |
[TableGen] Factor out timer code into a new `TGTimer` class (#111054)
Factor out the timer related functionality from `RecordKeeper` to a new
`TGTimer` class in a new file.
|
#
a140931b |
| 01-Oct-2024 |
Rahul Joshi <rjoshi@nvidia.com> |
[TableGen] Change `getValueAsListOfDefs` to return const pointer vector (#110713)
Change `getValueAsListOfDefs` to return a vector of const Record
pointer, and remove `getValueAsListOfConstDefs` th
[TableGen] Change `getValueAsListOfDefs` to return const pointer vector (#110713)
Change `getValueAsListOfDefs` to return a vector of const Record
pointer, and remove `getValueAsListOfConstDefs` that was added as a
transition aid.
This is a part of effort to have better const correctness in TableGen
backends:
https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
show more ...
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Revision tags: llvmorg-19.1.1 |
|
#
d109636c |
| 20-Sep-2024 |
Rahul Joshi <rjoshi@nvidia.com> |
[LLVM][TableGen] Change GISelCombinerEmitter to use const RecordKeeper (#109187)
Change GISelCombinerEmitter to use const RecordKeeper.
This is a part of effort to have better const correctness i
[LLVM][TableGen] Change GISelCombinerEmitter to use const RecordKeeper (#109187)
Change GISelCombinerEmitter to use const RecordKeeper.
This is a part of effort to have better const correctness in TableGen
backends:
https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
show more ...
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Revision tags: llvmorg-19.1.0 |
|
#
4b676e17 |
| 07-Sep-2024 |
Kazu Hirata <kazu@google.com> |
[TableGen] Avoid repeated hash lookups (NFC) (#107669)
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Revision tags: llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2 |
|
#
972c0292 |
| 01-Aug-2024 |
Pierre van Houtryve <pierre.vanhoutryve@amd.com> |
[GlobalISel][TableGen] MIR Pattern Variadics (#100563)
Allow for matching & rewriting a variable number of arguments in an
instructions.
Solves #87459
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Revision tags: llvmorg-19.1.0-rc1, llvmorg-20-init |
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#
c025bd1f |
| 20-Jun-2024 |
Fangrui Song <i@maskray.me> |
[TableGen,GlobalISel] Use MapVector to stabilize iteration order
Otherwise llvm/test/TableGen/GlobalISelCombinerEmitter/type-inference.td could fail when llvm::hash_value(StringRef) changes.
Fix #6
[TableGen,GlobalISel] Use MapVector to stabilize iteration order
Otherwise llvm/test/TableGen/GlobalISelCombinerEmitter/type-inference.td could fail when llvm::hash_value(StringRef) changes.
Fix #66377
show more ...
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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6 |
|
#
7d810623 |
| 16-May-2024 |
Pierre van Houtryve <pierre.vanhoutryve@amd.com> |
[GlobalISel] Refactor Combiner MatchData & Apply C++ Code Handling (#92239)
Combiners that use C++ code in their "apply" pattern only use that. They
never mix it with MIR patterns as that has littl
[GlobalISel] Refactor Combiner MatchData & Apply C++ Code Handling (#92239)
Combiners that use C++ code in their "apply" pattern only use that. They
never mix it with MIR patterns as that has little added value.
This patch restricts C++ apply code so that if C++ is used, we cannot
use MIR patterns or builtins with it. Adding this restriction allows us
to merge calls to match and apply C++ code together, which in turns
makes it so we can just have MatchData variables on the stack.
So before, we would have
```
GIM_CheckCxxInsnPredicate // match
GIM_CheckCxxInsnPredicate // apply
GIR_Done
```
Alongside a massive C++ struct holding the MatchData of all rules
possible (which was a big space/perf issue).
Now we just have
```
GIR_DoneWithCustomAction
```
And the function being ran just does
```
unsigned SomeMatchData;
if (match(SomeMatchData))
apply(SomeMatchData)
```
This approach solves multiple issues in one:
- MatchData handling is greatly simplified and more efficient, "don't
pay for what you don't use"
- We reduce the size of the match table
- Calling C++ code has a certain overhead (we need a switch), and this
overhead is only paid once now.
Handling of C++ code inside PatFrags is unchanged though, that still
emits a `GIM_CheckCxxInsnPredicate`. This is completely fine as they
can't use MatchDatas.
show more ...
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Revision tags: llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3 |
|
#
360f7f56 |
| 29-Mar-2024 |
Shilei Tian <i@tianshilei.me> |
[GlobalISel] Call `setInstrAndDebugLoc` before `tryCombineAll` (#86993)
This can remove all unnecessary redundant calls in each combiner.
|
#
4f9aab2b |
| 27-Mar-2024 |
Pierre van Houtryve <pierre.vanhoutryve@amd.com> |
[NFC][TableGen][GlobalISel] Move MIR pattern parsing out of combiner (#86789)
Reland of cfa0833ccc7450a322e709583e894e4c96ce682e
|
#
fa3d789d |
| 25-Mar-2024 |
Pierre van Houtryve <pierre.vanhoutryve@amd.com> |
[RFC][TableGen] Restructure TableGen Source (#80847)
Refactor of the llvm-tblgen source into:
- a "Basic" library, which contains the bare minimum utilities to build
`llvm-min-tablegen`
- a "Comm
[RFC][TableGen] Restructure TableGen Source (#80847)
Refactor of the llvm-tblgen source into:
- a "Basic" library, which contains the bare minimum utilities to build
`llvm-min-tablegen`
- a "Common" library which contains all of the helpers for TableGen
backends. Such helpers can be shared by more than one backend, and even
unit tested (e.g. CodeExpander is, maybe we can add more over time)
Fixes #80647
show more ...
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Revision tags: llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3 |
|
#
f723260a |
| 14-Feb-2024 |
Jay Foad <jay.foad@amd.com> |
[TableGen] Stop using make_pair and make_tuple. NFC. (#81730)
These are unnecessary since C++17.
|
Revision tags: llvmorg-18.1.0-rc2 |
|
#
991d04d7 |
| 05-Feb-2024 |
pvanhout <pierre.vanhoutryve@amd.com> |
Revert "[NFC][TableGen][GlobalISel] Move MIR Pattern Parsing out of Combiner Impl (#80257)"
This reverts commit cfa0833ccc7450a322e709583e894e4c96ce682e.
|
#
cfa0833c |
| 05-Feb-2024 |
Pierre van Houtryve <pierre.vanhoutryve@amd.com> |
[NFC][TableGen][GlobalISel] Move MIR Pattern Parsing out of Combiner Impl (#80257)
This just moves code around so the MIR pattern parsing logic is
separated and reusable.
|
#
7ec996d4 |
| 01-Feb-2024 |
Pierre van Houtryve <pierre.vanhoutryve@amd.com> |
[GlobalISel][TableGen] Support Intrinsics in MIR Patterns (#79278)
|
Revision tags: llvmorg-18.1.0-rc1, llvmorg-19-init |
|
#
8e8c954a |
| 13-Jan-2024 |
Sergei Barannikov <barannikov88@gmail.com> |
[GISel] Erase the root instruction after emitting all its potential uses (#77494)
This tries to fix a bug by resolving a few FIXMEs. The bug is that
`EraseInstAction` is emitted after emitting the
[GISel] Erase the root instruction after emitting all its potential uses (#77494)
This tries to fix a bug by resolving a few FIXMEs. The bug is that
`EraseInstAction` is emitted after emitting the _first_ `BuildMIAction`,
which is too early because the erased instruction may still be used by
subsequent `BuildMIAction`s (in particular, by `CopyRenderer`).
An example of the bug (from `match-table-operand-types.td`):
```
def InstTest0 : GICombineRule<
(defs root:$a),
(match (G_MUL i32:$x, i32:$b, i32:$c),
(G_MUL $a, i32:$b, i32:$x)),
(apply (G_ADD i64:$tmp, $b, i32:$c),
(G_ADD i8:$a, $b, i64:$tmp))>;
GIR_EraseFromParent, /*InsnID*/0,
GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD),
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // b
GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
```
Here, the root instruction is destroyed before copying its operands ('a'
and 'b') to the new instruction.
The solution is to emit `EraseInstAction` for the root instruction as
the last action in the emission pipeline.
show more ...
|
#
06286a55 |
| 09-Jan-2024 |
Sergei Barannikov <barannikov88@gmail.com> |
[GISel] Add RegState::Define to temporary defs in apply patterns (#77425)
Previously, registers created for temporary defs in apply patterns were
rendered as uses, resulting in machine verifier err
[GISel] Add RegState::Define to temporary defs in apply patterns (#77425)
Previously, registers created for temporary defs in apply patterns were
rendered as uses, resulting in machine verifier errors.
show more ...
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#
f92b928b |
| 09-Jan-2024 |
Sergei Barannikov <barannikov88@gmail.com> |
[GISel] Infer the type of an immediate when there is one element in TEC (#77399)
When there is just one element in the type equivalence class (TEC),
`inferNamedOperandType` fails because it does no
[GISel] Infer the type of an immediate when there is one element in TEC (#77399)
When there is just one element in the type equivalence class (TEC),
`inferNamedOperandType` fails because it does not consider the passed
operand as a suitable one. This is incorrect when inferring the type of
an (unnamed) immediate operand.
show more ...
|
#
dd0973be |
| 28-Nov-2023 |
Pierre van Houtryve <pierre.vanhoutryve@amd.com> |
[TableGen] Split GlobalISelCombinerEmitter into multiple files (#73325)
Split MatchDataInfo, CXXPredicates and the Pattern hierarchy into their
own files.
This should help with maintenance a bit
[TableGen] Split GlobalISelCombinerEmitter into multiple files (#73325)
Split MatchDataInfo, CXXPredicates and the Pattern hierarchy into their
own files.
This should help with maintenance a bit, and make the API easier to
navigate.
I hope this encourages a bit more experimentation with MIR patterns,
e.g. I'd like to try getting them in ISel at some point.
Currently, this is pretty much only moving code around. There is no
significant refactoring in there.
I want to split the Combiner backend even more at some point though,
e.g. by separating the TableGen parsing logic into yet another file so
other backends could very easily parse patterns themselves.
Note: I moved the responsibility of managing string lifetimes into the
backend instead of the Pattern class.
e.g. Before you'd do `P.addOperand(Name)` but now it's
`P.addOperand(insertStrRef(Name))`.
I verified this was done correctly by running the tests with UBSan/ASan.
show more ...
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Revision tags: llvmorg-17.0.6, llvmorg-17.0.5 |
|
#
96e97864 |
| 08-Nov-2023 |
Pierre van Houtryve <pierre.vanhoutryve@amd.com> |
[TableGen][GlobalISel] Add MIFlags matching & rewriting (#71179)
Also disables generation of MutateOpcode. It's almost never used in
combiners anyway.
If we really want to use it, it needs to be i
[TableGen][GlobalISel] Add MIFlags matching & rewriting (#71179)
Also disables generation of MutateOpcode. It's almost never used in
combiners anyway.
If we really want to use it, it needs to be investigated & properly
fixed (see TODO)
Fixes #70780
show more ...
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#
573fa770 |
| 08-Nov-2023 |
Pierre van Houtryve <pierre.vanhoutryve@amd.com> |
[TableGen][GlobalISel] Add rule-wide type inference (#66377)
The inference is trivial and leverages the MCOI OperandTypes encoded in
CodeGenInstructions to infer types across patterns in a CombineR
[TableGen][GlobalISel] Add rule-wide type inference (#66377)
The inference is trivial and leverages the MCOI OperandTypes encoded in
CodeGenInstructions to infer types across patterns in a CombineRule.
It's thus very limited and only supports CodeGenInstructions (but that's the
main use case so it's fine).
We only try to infer untyped operands in apply patterns when they're
temp reg defs, or immediates. Inference always outputs a `GITypeOf<$x>` where
$x is a named operand from a match pattern.
This allows us to drop the `GITypeOf` in most cases without any errors.
show more ...
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#
b26e6a8e |
| 31-Oct-2023 |
Pierre van Houtryve <pierre.vanhoutryve@amd.com> |
[GlobalISel] Add `GITypeOf` special type (#66079)
Allows creating a register/immediate that uses the same type as a
matched operand.
|