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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2 |
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2aafb73f |
| 08-Apr-2023 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Actually change to the temporary directory in test
Hopefully fixes issue #61132
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Revision tags: llvmorg-16.0.1 |
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546daf1a |
| 03-Apr-2023 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Try running test in temporary directory
Attempt to fix issue #61761
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Revision tags: llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1 |
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9a501ebe |
| 28-Jan-2023 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Add REQUIRES: default_triple to test
Allegedly fixes test failure if there are no targets built.
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Revision tags: llvmorg-17-init |
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d78b4c44 |
| 20-Jan-2023 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Fix default handling of intermediate format
Bitcode inputs should produce bitcode intermediates by
default.
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Revision tags: llvmorg-15.0.7 |
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d8fb46ee |
| 21-Dec-2022 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Remove test dependence on registered targets
This reverts e4b126cc2d33033a5538d72a88f6aa153ac8b757 and
e57ab8fe91f06e71d3de2df07e6c7efd2f0c6078.
This previously depended on where the t
llvm-reduce: Remove test dependence on registered targets
This reverts e4b126cc2d33033a5538d72a88f6aa153ac8b757 and
e57ab8fe91f06e71d3de2df07e6c7efd2f0c6078.
This previously depended on where the target happened to construct (or
not) the MachineFunctionInfo during the initial MIR construction. Now
that the MachineFunctionInfo is consistently constructed at
MachineFunction construction time, this should always work.
show more ...
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Revision tags: llvmorg-15.0.6, llvmorg-15.0.5 |
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e4b126cc |
| 02-Nov-2022 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Require x86 to run file ouput test
The MIR test somewhat depends on target support.
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e57ab8fe |
| 02-Nov-2022 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Add explicit triple to test
Some host targets are managing to get through MIR parsing
without constructing their MachineFunctionInfo.
Fixes at least SystemZ and SPARC (issue 58768)
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Revision tags: llvmorg-15.0.4 |
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4e21bc0c |
| 29-Oct-2022 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Drop guessing output format based on file extension
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3c436ab0 |
| 26-Oct-2022 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Support emitting bitcode for final result
Previously, this unconditionally emitted text IR. I ran
into a bug that manifested in broken disassembly, so the
desired output was the bitcode
llvm-reduce: Support emitting bitcode for final result
Previously, this unconditionally emitted text IR. I ran
into a bug that manifested in broken disassembly, so the
desired output was the bitcode format. If the input format
was binary bitcode, the requested output file ends in .bc,
or an explicit -output-bitcode option was used, emit bitcode.
show more ...
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