[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)


This is based on other targets like PPC/AArch64 and some experiments.

This PR will only enable bidirectional schedu

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)


This is based on other targets like PPC/AArch64 and some experiments.

This PR will only enable bidirectional scheduling and tracking register
pressure.

Disclaimer: I haven't tested it on many cores, maybe we should make
some options being features. I believe downstreams must have tried
this before, so feedbacks are welcome.

show more ...

[RISCV][CFI] add function epilogue cfi information (#110810)

This patch adds CFI instructions in the function epilogue.

Before patch:
addi sp, s0, -32
ld ra, 24(sp) # 8-byte Folded Reload
ld s

[RISCV][CFI] add function epilogue cfi information (#110810)

This patch adds CFI instructions in the function epilogue.

Before patch:
addi sp, s0, -32
ld ra, 24(sp) # 8-byte Folded Reload
ld s0, 16(sp) # 8-byte Folded Reload
ld s1, 8(sp) # 8-byte Folded Reload
addi sp, sp, 32
ret

After patch:
addi sp, s0, -32
.cfi_def_cfa sp, 32
ld ra, 24(sp) # 8-byte Folded Reload
ld s0, 16(sp) # 8-byte Folded Reload
ld s1, 8(sp) # 8-byte Folded Reload
.cfi_restore ra
.cfi_restore s0
.cfi_restore s1
addi sp, sp, 32
.cfi_def_cfa_offset 0
ret

This functionality is already present in `riscv-gcc`, but it’s not in
`clang` and this slightly impairs the `lldb` debugging experience, e.g.
backtrace.

show more ...

[RISCV] Enable store clustering by default (#73796)

Builds on #73789, enabling store clustering by default using the same
heuristic.

[RISCV] Enable load clustering by default (#73789)

We believe this is neutral or slightly better in the majority of cases.

[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)

R_RISCV_CALL/R_RISCV_CALL_PLT distinction is not necessary and
R_RISCV_CALL has been deprecated. Since https://reviews.llvm.org/D132530

[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)

R_RISCV_CALL/R_RISCV_CALL_PLT distinction is not necessary and
R_RISCV_CALL has been deprecated. Since https://reviews.llvm.org/D132530
`call foo` assembles to R_RISCV_CALL_PLT. The `@plt` suffix is not
useful and can be removed now (matching AArch64 and PowerPC).

GNU assembler assembles `call foo` to RISCV_CALL_PLT since 2022-09
(70f35d72ef04cd23771875c1661c9975044a749c).

Without this patch, unconditionally changing MO_CALL to MO_PLT could
create `jump .L1@plt, a0`, which is invalid in LLVM integrated assembler
and GNU assembler.

show more ...

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

This reverts commit 2501ae58e3bb9a70d279a56d7b3a0ed70a8a852c.

Reverted due to various buildbot failures.

[CodeGen] Really renumber slot indexes before register allocation (#67038)

PR #66334 tried to renumber slot indexes before register allocation, but
the numbering was still affected by list entries

[CodeGen] Really renumber slot indexes before register allocation (#67038)

PR #66334 tried to renumber slot indexes before register allocation, but
the numbering was still affected by list entries for instructions which
had been erased. Fix this to make the register allocator's live range
length heuristics even less dependent on the history of how instructions
have been added to and removed from SlotIndexes's maps.

show more ...

[RISCV] Strip W suffix from ADDIW (#68425)

The motivation of this change is simply to reduce test duplication. As
can be seen in the (massive) test delta, we have many tests whose output
differ on

[RISCV] Strip W suffix from ADDIW (#68425)

The motivation of this change is simply to reduce test duplication. As
can be seen in the (massive) test delta, we have many tests whose output
differ only due to the use of addi on rv32 vs addiw on rv64 when the
high bits are don't care.

As an aside, we don't need to worry about the non-zero immediate
restriction on the compressed variants because we're not directly
forming the compressed variants. If we happen to get a zero immediate
for the ADDI, then either a later optimization will strip the useless
instruction or the encoder is responsible for not compressing the
instruction.

show more ...

[CodeGen] Renumber slot indexes before register allocation (#66334)

RegAllocGreedy uses SlotIndexes::getApproxInstrDistance to approximate
the length of a live range for its heuristics. Renumbering

[CodeGen] Renumber slot indexes before register allocation (#66334)

RegAllocGreedy uses SlotIndexes::getApproxInstrDistance to approximate
the length of a live range for its heuristics. Renumbering all slot
indexes with the default instruction distance ensures that this estimate
will be as accurate as possible, and will not depend on the history of
how instructions have been added to and removed from SlotIndexes's maps.

This also means that enabling -early-live-intervals, which runs the
SlotIndexes analysis earlier, will not cause large amounts of churn due
to different register allocator decisions.

show more ...

[RA] Split a virtual register in cold blocks if it is not assigned preferred physical register

If a virtual register is not assigned preferred physical register, it means some
COPY instructions will

[RA] Split a virtual register in cold blocks if it is not assigned preferred physical register

If a virtual register is not assigned preferred physical register, it means some
COPY instructions will be changed to real register move instructions. In this
case we can try to split the virtual register in colder blocks, if success, the
original COPY instructions can be deleted, and the new COPY instructions in
colder blocks will be generated as register move instructions. It results in
fewer dynamic register move instructions executed.

The new test case split-reg-with-hint.ll gives an example, the hot path contains
24 instructions without this patch, now it is only 4 instructions with this
patch.

Differential Revision: https://reviews.llvm.org/D156491

show more ...

[RISCV] Add special case for i32 uaddo X, -1 on RV64.

uaddo X, -1 over flows if X is non-zero.

Matches what we do i32 uaddo X, -1 on RV32.

Fixes #61891.

[RISCV] Add i32 uaddo X, -1 test case. NFC

[LegalizeTypes][TargetLowering][RISCV] Fix regressions from D146786.

Add some special cases for UADDO to recover codegen after D146786.

Reviewed By: reames, liaolucy

Differential Revision: https:/

[LegalizeTypes][TargetLowering][RISCV] Fix regressions from D146786.

Add some special cases for UADDO to recover codegen after D146786.

Reviewed By: reames, liaolucy

Differential Revision: https://reviews.llvm.org/D146789

show more ...

[CodeGenPrepare][RISCV] Correct the MathUsed flag for shouldFormOverflowOp

For add, if we match the constant edge case the add isn't used by
the compare so we shouldn't check for 2 users.

For sub,

[CodeGenPrepare][RISCV] Correct the MathUsed flag for shouldFormOverflowOp

For add, if we match the constant edge case the add isn't used by
the compare so we shouldn't check for 2 users.

For sub, the compare is not a user of the sub so the math is
used if the sub has any users.

This regresses RISC-V which I will work on other patches for.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D146786

show more ...

[LegalizeTypes][RISCV] Add a special case for (add X, -1) to ExpandIntRes_ADDSUB

On targets without ADDCARRY or ADDE, we need to emit a separate
SETCC to determine carry from the low half to the h

[LegalizeTypes][RISCV] Add a special case for (add X, -1) to ExpandIntRes_ADDSUB

On targets without ADDCARRY or ADDE, we need to emit a separate
SETCC to determine carry from the low half to the high half.
The high half is calculated by a series of ADDs.

When RHSLo and RHSHi are -1, without this patch, we get:
Hi = (add (add LHSHi,(setult Lo, LHSLo), -1)
Where as with the patch we get:
Hi = (sub LHSHi, (seteq LHSLo, 0))

Only RHSLo is -1 we can instead do (setne Lo, 0).

Similar to gcc: https://godbolt.org/z/M83f6rz39

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D146635

show more ...

[RISCV] Return false from shouldFormOverflowOp when type is i8 and i16

i8 and i16 are not using overflow.
Reduce the number of zero extension instructions.

To reduce the uncertainty of the unknown,

[RISCV] Return false from shouldFormOverflowOp when type is i8 and i16

i8 and i16 are not using overflow.
Reduce the number of zero extension instructions.

To reduce the uncertainty of the unknown,
most of the checks of the virtual function are kept

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143646

show more ...

[RISCV] Add more testcases for overflow-intrinsics.ll

[LegalizeTypes] Add a special case for (add X, 1) to ExpandIntRes_ADDSUB.

On targets without ADDCARRY or ADDE, we need to emit a separate
SETCC to determine carry from the low half to the high half.

[LegalizeTypes] Add a special case for (add X, 1) to ExpandIntRes_ADDSUB.

On targets without ADDCARRY or ADDE, we need to emit a separate
SETCC to determine carry from the low half to the high half. Usually
we do (setult Lo, LHSLo). If RHSLo is 1 we can instead do (seteq Lo, 0).
This can reduce the live range of LHSLo.

show more ...

[LegalizeTypes][RISCV] Add a special case to ExpandIntRes_UADDSUBO for (uaddo X, 1).

On targets that lack ADDCARRY support we split a wide uaddo into
an ADD and a SETCC that both need to be split.

[LegalizeTypes][RISCV] Add a special case to ExpandIntRes_UADDSUBO for (uaddo X, 1).

On targets that lack ADDCARRY support we split a wide uaddo into
an ADD and a SETCC that both need to be split.

For (uaddo X, 1) we can observe that when the add overflows the result
will be 0. We can emit (seteq (or Lo, Hi), 0) to detect this.

This improves D142071.

There is an alternative here. We could use either ~(lo(X) & hi(X)) == 0 or
(lo(X) & hi(X)) == -1 before the addition. That would be closer to the
code before D142071.

Reviewed By: liaolucy

Differential Revision: https://reviews.llvm.org/D144614

show more ...

[RISCV] Add precommit tests for D143646