[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)

This change implements support for the `cr` and `cf` register
constraints (which allocate a RVC GPR or RVC FPR respectively), and th

[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)

This change implements support for the `cr` and `cf` register
constraints (which allocate a RVC GPR or RVC FPR respectively), and the
`N` modifier (which prints the raw encoding of a register rather than
the name).

The intention behind these additions is to make it easier to use inline
assembly when assembling raw instructions that are not supported by the
compiler, for instance when experimenting with new instructions or when
supporting proprietary extensions outside the toolchain.

These implement part of my proposal in riscv-non-isa/riscv-c-api-doc#92

As part of the implementation, I felt there was not enough coverage of
inline assembly and the "in X" floating-point extensions, so I have
added more regression tests around these configurations.

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[RISCV][NFC] Move tests of inline asm memory constraints to separate file

We will need to check the output of medium code model.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org

[RISCV][NFC] Move tests of inline asm memory constraints to separate file

We will need to check the output of medium code model.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D157965

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[RISCV] Don't allow X0 to be used for 'r' constraint in inline assembly

Some instructions treat x0 as a special encoding rather than as a
value of 0. Since we don't parse the inline assembly to know

[RISCV] Don't allow X0 to be used for 'r' constraint in inline assembly

Some instructions treat x0 as a special encoding rather than as a
value of 0. Since we don't parse the inline assembly to know what
the instruction is, chooser the safest option of never using x0.

Fixes #63747.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D154744

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[RISCV] Handle "o" inline asm memory constraint

This is the same as D100412.

We just found the same crash when we tried to compile some packages
like mariadb, php, etc.

For constraint "o", it mean

[RISCV] Handle "o" inline asm memory constraint

This is the same as D100412.

We just found the same crash when we tried to compile some packages
like mariadb, php, etc.

For constraint "o", it means "A memory operand is allowed, but
only if the address is offsettable". So I think it can be handled
just like constraint "m" for RISCV target.

And we print verbose information when unsupported constraints occur.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D151979

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[RISCV] Lower inline asm m with offset to register+imm.

As part of D145584, we noticed that llvm was generating suboptimal code
for constraint m when the operand can be be lowered to reg+imm form: i

[RISCV] Lower inline asm m with offset to register+imm.

As part of D145584, we noticed that llvm was generating suboptimal code
for constraint m when the operand can be be lowered to reg+imm form: it
was being selected as a single register rather than register+imm. This
caused an unnecessary 'addi' to be gen for each m constraint.

This patch changes llvm to select register+imm. This might generate code
that cannot be assembled, but matches gcc's behavior.

Reviewed By: craig.topper, kito-cheng

Differential Revision: https://reviews.llvm.org/D146245

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[RISCV] Fix missing addi in test to validate lower inline asm m with offset

[RISCV] Added tests to validate lower inline asm m and A with offsets

[RISCV] Convert some tests to opaque pointers (NFC)

[RISCV] Don't advertise i32->i64 zextload as free for RV64.

The zextload hook is only used to determine whether to insert a
zero_extend or any_extend for narrow types leaving a basic block.
Returnin

[RISCV] Don't advertise i32->i64 zextload as free for RV64.

The zextload hook is only used to determine whether to insert a
zero_extend or any_extend for narrow types leaving a basic block.
Returning true from this hook tends to cause any load whose output
leaves the basic block to become an LWU instead of an LW.

Since we tend to prefer sexts for i32 compares on RV64, this can
cause extra sext.w instructions to be created in other basic blocks.

If we use LW instead of LWU this gives the MIR pass from D116397
a better chance of removing them.

Another option might be to teach getPreferredExtendForValue in
FunctionLoweringInfo.cpp about our preference for sign_extend of
i32 compares. That would cause SIGN_EXTEND to be chosen for any
value used by a compare instead of using the isZExtFree heuristic.
That will require code to convert from the llvm::Type* to EVT/MVT
as well as querying the type legalization actions to get the
promoted type in order to call TargetLowering::isSExtCheaperThanZExt.
That seemed like many extra steps when no other target wants it.
Though it would avoid us needing to lean on the MIR pass in some cases.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D116567

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[Tests] Add elementtype attribute to indirect inline asm operands (NFC)

This updates LLVM tests for D116531 by adding elementtype attributes
to operands that correspond to indirect asm constraints.

[MC][RISCV] Set UseIntegratedAssembler to true

to align with most other targets. Also, -fintegrated-as is the default
for clang -target riscv*.

[RISCV] Fix test for inline asm z constraint modifier

Summary: Use an `i` constraint in the test, to correctly trigger the code for
handling the `z` constraint modifier.

Reviewers: asb, lenary, jrt

[RISCV] Fix test for inline asm z constraint modifier

Summary: Use an `i` constraint in the test, to correctly trigger the code for
handling the `z` constraint modifier.

Reviewers: asb, lenary, jrtc27
Reviewed By: lenary, jrtc27
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72134

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[RISCV] Handle globals and block addresses in asm operands

Summary: These seem to be the machine operand types currently needed by the
RISC-V target.

Reviewers: asb, lenary
Reviewed By: lenary
Tags

[RISCV] Handle globals and block addresses in asm operands

Summary: These seem to be the machine operand types currently needed by the
RISC-V target.

Reviewers: asb, lenary
Reviewed By: lenary
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72275

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[RISCV] Fix a couple of tests' CHECKs

llvm-svn: 370466

[RISCV] Lower inline asm constraint A for RISC-V

This allows arguments with the constraint A to be lowered to input nodes
for RISC-V, which implies a memory address stored in a register.

This patch

[RISCV] Lower inline asm constraint A for RISC-V

This allows arguments with the constraint A to be lowered to input nodes
for RISC-V, which implies a memory address stored in a register.

This patch adds the minimal amount of code required to get operands with
the right constraints to compile.

https://reviews.llvm.org/D54296

llvm-svn: 369095

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[RISCV] Support z and i operand modifiers

Differential Revision: https://reviews.llvm.org/D57792
Patch by James Clarke.

llvm-svn: 365291

[RISCV] Fix inline-asm.ll test by adding nounwind attribute

This test failed since CFI directive support was added in r361320.

llvm-svn: 363123

[RISCV] Lower inline asm constraints I, J & K for RISC-V

This validates and lowers arguments to inline asm nodes which have the
constraints I, J & K, with the following semantics (equivalent to GCC)

[RISCV] Lower inline asm constraints I, J & K for RISC-V

This validates and lowers arguments to inline asm nodes which have the
constraints I, J & K, with the following semantics (equivalent to GCC):

I: Any 12-bit signed immediate.
J: Immediate integer zero only.
K: Any 5-bit unsigned immediate.

Differential Revision: https://reviews.llvm.org/D54093

llvm-svn: 363054

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[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV

r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives.

llv

[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV

r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives.

llvm-svn: 361493

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[RISCV][NFC] Add RV64I CHECK lines to inline-asm.ll test

llvm-svn: 354028

[RISCV] Peephole optimisation for load/store of global values or constant addresses

(load (add base, off), 0) -> (load base, off)
(store val, (add base, off)) -> (store val, base, off)

This is simi

[RISCV] Peephole optimisation for load/store of global values or constant addresses

(load (add base, off), 0) -> (load base, off)
(store val, (add base, off)) -> (store val, base, off)

This is similar to an equivalent peephole optimisation in PPCISelDAGToDAG.

llvm-svn: 327831

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[RISCV] Implement frame pointer elimination

llvm-svn: 322839

[RISCV] Add basic support for inline asm constraints

llvm-svn: 322217