Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3 |
|
#
228f88fd |
| 18-Oct-2024 |
Sam Elliott <quic_aelliott@quicinc.com> |
[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)
This change implements support for the `cr` and `cf` register
constraints (which allocate a RVC GPR or RVC FPR respectively), and th
[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)
This change implements support for the `cr` and `cf` register
constraints (which allocate a RVC GPR or RVC FPR respectively), and the
`N` modifier (which prints the raw encoding of a register rather than
the name).
The intention behind these additions is to make it easier to use inline
assembly when assembling raw instructions that are not supported by the
compiler, for instance when experimenting with new instructions or when
supporting proprietary extensions outside the toolchain.
These implement part of my proposal in riscv-non-isa/riscv-c-api-doc#92
As part of the implementation, I felt there was not enough coverage of
inline assembly and the "in X" floating-point extensions, so I have
added more regression tests around these configurations.
show more ...
|
Revision tags: llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3 |
|
#
a3b11ce7 |
| 21-Aug-2023 |
wangpc <wangpengcheng.pp@bytedance.com> |
[RISCV][NFC] Move tests of inline asm memory constraints to separate file
We will need to check the output of medium code model.
Reviewed By: wangpc
Differential Revision: https://reviews.llvm.org
[RISCV][NFC] Move tests of inline asm memory constraints to separate file
We will need to check the output of medium code model.
Reviewed By: wangpc
Differential Revision: https://reviews.llvm.org/D157965
show more ...
|
Revision tags: llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init |
|
#
dbd47c44 |
| 10-Jul-2023 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Don't allow X0 to be used for 'r' constraint in inline assembly
Some instructions treat x0 as a special encoding rather than as a value of 0. Since we don't parse the inline assembly to know
[RISCV] Don't allow X0 to be used for 'r' constraint in inline assembly
Some instructions treat x0 as a special encoding rather than as a value of 0. Since we don't parse the inline assembly to know what the instruction is, chooser the safest option of never using x0.
Fixes #63747.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D154744
show more ...
|
Revision tags: llvmorg-16.0.6 |
|
#
26e41a80 |
| 06-Jun-2023 |
wangpc <pc.wang@linux.alibaba.com> |
[RISCV] Handle "o" inline asm memory constraint
This is the same as D100412.
We just found the same crash when we tried to compile some packages like mariadb, php, etc.
For constraint "o", it mean
[RISCV] Handle "o" inline asm memory constraint
This is the same as D100412.
We just found the same crash when we tried to compile some packages like mariadb, php, etc.
For constraint "o", it means "A memory operand is allowed, but only if the address is offsettable". So I think it can be handled just like constraint "m" for RISCV target.
And we print verbose information when unsupported constraints occur.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D151979
show more ...
|
Revision tags: llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1 |
|
#
6217f472 |
| 31-Mar-2023 |
Mikhail R. Gadelha <mikhail@igalia.com> |
[RISCV] Lower inline asm m with offset to register+imm.
As part of D145584, we noticed that llvm was generating suboptimal code for constraint m when the operand can be be lowered to reg+imm form: i
[RISCV] Lower inline asm m with offset to register+imm.
As part of D145584, we noticed that llvm was generating suboptimal code for constraint m when the operand can be be lowered to reg+imm form: it was being selected as a single register rather than register+imm. This caused an unnecessary 'addi' to be gen for each m constraint.
This patch changes llvm to select register+imm. This might generate code that cannot be assembled, but matches gcc's behavior.
Reviewed By: craig.topper, kito-cheng
Differential Revision: https://reviews.llvm.org/D146245
show more ...
|
Revision tags: llvmorg-16.0.0 |
|
#
185ea867 |
| 16-Mar-2023 |
Mikhail R. Gadelha <mikhail@igalia.com> |
[RISCV] Fix missing addi in test to validate lower inline asm m with offset
|
#
4bbee03d |
| 16-Mar-2023 |
Mikhail R. Gadelha <mikhail@igalia.com> |
[RISCV] Added tests to validate lower inline asm m and A with offsets
|
Revision tags: llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7 |
|
#
1456b686 |
| 19-Dec-2022 |
Nikita Popov <npopov@redhat.com> |
[RISCV] Convert some tests to opaque pointers (NFC)
|
Revision tags: llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2 |
|
#
75117fb3 |
| 06-Jan-2022 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Don't advertise i32->i64 zextload as free for RV64.
The zextload hook is only used to determine whether to insert a zero_extend or any_extend for narrow types leaving a basic block. Returnin
[RISCV] Don't advertise i32->i64 zextload as free for RV64.
The zextload hook is only used to determine whether to insert a zero_extend or any_extend for narrow types leaving a basic block. Returning true from this hook tends to cause any load whose output leaves the basic block to become an LWU instead of an LW.
Since we tend to prefer sexts for i32 compares on RV64, this can cause extra sext.w instructions to be created in other basic blocks.
If we use LW instead of LWU this gives the MIR pass from D116397 a better chance of removing them.
Another option might be to teach getPreferredExtendForValue in FunctionLoweringInfo.cpp about our preference for sign_extend of i32 compares. That would cause SIGN_EXTEND to be chosen for any value used by a compare instead of using the isZExtFree heuristic. That will require code to convert from the llvm::Type* to EVT/MVT as well as querying the type legalization actions to get the promoted type in order to call TargetLowering::isSExtCheaperThanZExt. That seemed like many extra steps when no other target wants it. Though it would avoid us needing to lean on the MIR pass in some cases.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D116567
show more ...
|
#
f430c1eb |
| 06-Jan-2022 |
Nikita Popov <npopov@redhat.com> |
[Tests] Add elementtype attribute to indirect inline asm operands (NFC)
This updates LLVM tests for D116531 by adding elementtype attributes to operands that correspond to indirect asm constraints.
|
Revision tags: llvmorg-13.0.1-rc1, llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1, llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2, llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2, llvmorg-11.1.0-rc1, llvmorg-11.0.1, llvmorg-11.0.1-rc2, llvmorg-11.0.1-rc1, llvmorg-11.0.0, llvmorg-11.0.0-rc6, llvmorg-11.0.0-rc5, llvmorg-11.0.0-rc4, llvmorg-11.0.0-rc3, llvmorg-11.0.0-rc2, llvmorg-11.0.0-rc1, llvmorg-12-init |
|
#
4d5fd0ee |
| 13-Jul-2020 |
Fangrui Song <maskray@google.com> |
[MC][RISCV] Set UseIntegratedAssembler to true
to align with most other targets. Also, -fintegrated-as is the default for clang -target riscv*.
|
Revision tags: llvmorg-10.0.1, llvmorg-10.0.1-rc4, llvmorg-10.0.1-rc3, llvmorg-10.0.1-rc2, llvmorg-10.0.1-rc1, llvmorg-10.0.0, llvmorg-10.0.0-rc6, llvmorg-10.0.0-rc5, llvmorg-10.0.0-rc4, llvmorg-10.0.0-rc3, llvmorg-10.0.0-rc2, llvmorg-10.0.0-rc1 |
|
#
46e3edcc |
| 15-Jan-2020 |
Luís Marques <luismarques@lowrisc.org> |
[RISCV] Fix test for inline asm z constraint modifier
Summary: Use an `i` constraint in the test, to correctly trigger the code for handling the `z` constraint modifier.
Reviewers: asb, lenary, jrt
[RISCV] Fix test for inline asm z constraint modifier
Summary: Use an `i` constraint in the test, to correctly trigger the code for handling the `z` constraint modifier.
Reviewers: asb, lenary, jrtc27 Reviewed By: lenary, jrtc27 Tags: #llvm Differential Revision: https://reviews.llvm.org/D72134
show more ...
|
Revision tags: llvmorg-11-init |
|
#
043c5eaf |
| 13-Jan-2020 |
Luís Marques <luismarques@lowrisc.org> |
[RISCV] Handle globals and block addresses in asm operands
Summary: These seem to be the machine operand types currently needed by the RISC-V target.
Reviewers: asb, lenary Reviewed By: lenary Tags
[RISCV] Handle globals and block addresses in asm operands
Summary: These seem to be the machine operand types currently needed by the RISC-V target.
Reviewers: asb, lenary Reviewed By: lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D72275
show more ...
|
Revision tags: llvmorg-9.0.1, llvmorg-9.0.1-rc3, llvmorg-9.0.1-rc2, llvmorg-9.0.1-rc1, llvmorg-9.0.0, llvmorg-9.0.0-rc6, llvmorg-9.0.0-rc5, llvmorg-9.0.0-rc4 |
|
#
c2b3d527 |
| 30-Aug-2019 |
Luis Marques <luismarques@lowrisc.org> |
[RISCV] Fix a couple of tests' CHECKs
llvm-svn: 370466
|
Revision tags: llvmorg-9.0.0-rc3 |
|
#
7abf863f |
| 16-Aug-2019 |
Lewis Revill <lewis.revill@embecosm.com> |
[RISCV] Lower inline asm constraint A for RISC-V
This allows arguments with the constraint A to be lowered to input nodes for RISC-V, which implies a memory address stored in a register.
This patch
[RISCV] Lower inline asm constraint A for RISC-V
This allows arguments with the constraint A to be lowered to input nodes for RISC-V, which implies a memory address stored in a register.
This patch adds the minimal amount of code required to get operands with the right constraints to compile.
https://reviews.llvm.org/D54296
llvm-svn: 369095
show more ...
|
Revision tags: llvmorg-9.0.0-rc2, llvmorg-9.0.0-rc1, llvmorg-10-init, llvmorg-8.0.1, llvmorg-8.0.1-rc4 |
|
#
e1e036a3 |
| 08-Jul-2019 |
Alex Bradbury <asb@lowrisc.org> |
[RISCV] Support z and i operand modifiers
Differential Revision: https://reviews.llvm.org/D57792 Patch by James Clarke.
llvm-svn: 365291
|
Revision tags: llvmorg-8.0.1-rc3 |
|
#
aa6f2af4 |
| 12-Jun-2019 |
Alex Bradbury <asb@lowrisc.org> |
[RISCV] Fix inline-asm.ll test by adding nounwind attribute
This test failed since CFI directive support was added in r361320.
llvm-svn: 363123
|
#
28a5cadb |
| 11-Jun-2019 |
Lewis Revill <lewis.revill@embecosm.com> |
[RISCV] Lower inline asm constraints I, J & K for RISC-V
This validates and lowers arguments to inline asm nodes which have the constraints I, J & K, with the following semantics (equivalent to GCC)
[RISCV] Lower inline asm constraints I, J & K for RISC-V
This validates and lowers arguments to inline asm nodes which have the constraints I, J & K, with the following semantics (equivalent to GCC):
I: Any 12-bit signed immediate. J: Immediate integer zero only. K: Any 5-bit unsigned immediate.
Differential Revision: https://reviews.llvm.org/D54093
llvm-svn: 363054
show more ...
|
Revision tags: llvmorg-8.0.1-rc2 |
|
#
5dabe03b |
| 23-May-2019 |
Alex Bradbury <asb@lowrisc.org> |
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives.
llv
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives.
llvm-svn: 361493
show more ...
|
Revision tags: llvmorg-8.0.1-rc1, llvmorg-8.0.0, llvmorg-8.0.0-rc5, llvmorg-8.0.0-rc4, llvmorg-8.0.0-rc3 |
|
#
4efa0b67 |
| 14-Feb-2019 |
Alex Bradbury <asb@lowrisc.org> |
[RISCV][NFC] Add RV64I CHECK lines to inline-asm.ll test
llvm-svn: 354028
|
Revision tags: llvmorg-7.1.0, llvmorg-7.1.0-rc1, llvmorg-8.0.0-rc2, llvmorg-8.0.0-rc1, llvmorg-7.0.1, llvmorg-7.0.1-rc3, llvmorg-7.0.1-rc2, llvmorg-7.0.1-rc1, llvmorg-7.0.0, llvmorg-7.0.0-rc3, llvmorg-7.0.0-rc2, llvmorg-7.0.0-rc1, llvmorg-6.0.1, llvmorg-6.0.1-rc3, llvmorg-6.0.1-rc2, llvmorg-6.0.1-rc1, llvmorg-5.0.2, llvmorg-5.0.2-rc2 |
|
#
0171a9f4 |
| 19-Mar-2018 |
Alex Bradbury <asb@lowrisc.org> |
[RISCV] Peephole optimisation for load/store of global values or constant addresses
(load (add base, off), 0) -> (load base, off) (store val, (add base, off)) -> (store val, base, off)
This is simi
[RISCV] Peephole optimisation for load/store of global values or constant addresses
(load (add base, off), 0) -> (load base, off) (store val, (add base, off)) -> (store val, base, off)
This is similar to an equivalent peephole optimisation in PPCISelDAGToDAG.
llvm-svn: 327831
show more ...
|
Revision tags: llvmorg-5.0.2-rc1, llvmorg-6.0.0, llvmorg-6.0.0-rc3, llvmorg-6.0.0-rc2 |
|
#
7d6aa1f7 |
| 18-Jan-2018 |
Alex Bradbury <asb@lowrisc.org> |
[RISCV] Implement frame pointer elimination
llvm-svn: 322839
|
Revision tags: llvmorg-6.0.0-rc1 |
|
#
9330e644 |
| 10-Jan-2018 |
Alex Bradbury <asb@lowrisc.org> |
[RISCV] Add basic support for inline asm constraints
llvm-svn: 322217
|