[RISCV][CFI] add function epilogue cfi information (#110810)

This patch adds CFI instructions in the function epilogue.

Before patch:
addi sp, s0, -32
ld ra, 24(sp) # 8-byte Folded Reload
ld s

[RISCV][CFI] add function epilogue cfi information (#110810)

This patch adds CFI instructions in the function epilogue.

Before patch:
addi sp, s0, -32
ld ra, 24(sp) # 8-byte Folded Reload
ld s0, 16(sp) # 8-byte Folded Reload
ld s1, 8(sp) # 8-byte Folded Reload
addi sp, sp, 32
ret

After patch:
addi sp, s0, -32
.cfi_def_cfa sp, 32
ld ra, 24(sp) # 8-byte Folded Reload
ld s0, 16(sp) # 8-byte Folded Reload
ld s1, 8(sp) # 8-byte Folded Reload
.cfi_restore ra
.cfi_restore s0
.cfi_restore s1
addi sp, sp, 32
.cfi_def_cfa_offset 0
ret

This functionality is already present in `riscv-gcc`, but it’s not in
`clang` and this slightly impairs the `lldb` debugging experience, e.g.
backtrace.

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[RISCV] Support the large code model. (#70308)

Implement large code model for GlobalAddressSDNode and ExternalSymbolSDNode.

See discussion on
https://github.com/riscv-non-isa/riscv-elf-psabi-doc

[RISCV] Support the large code model. (#70308)

Implement large code model for GlobalAddressSDNode and ExternalSymbolSDNode.

See discussion on
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/388.

---------

Co-authored-by: Kuan-Lin Chen <rufus@andestech.com>

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[RISCV] Mark symbols used in inline asm for relocations as referenced (#104925)

Commit 5cd8d53cac00f taught RISCVMergeBaseOffset to handle inline asm,
however
there is at least one case uncovered

[RISCV] Mark symbols used in inline asm for relocations as referenced (#104925)

Commit 5cd8d53cac00f taught RISCVMergeBaseOffset to handle inline asm,
however
there is at least one case uncovered for integrated as.

In the example below compiler generates pcrel relocation
(mcmodel=medany)
```
volatile double double_val = 1.0;
void foo() {
asm volatile("fld f0, %0 \n\t" : : "m"(double_val) : "memory");
}
```

And fails with the folliwng error
```
error: could not find corresponding %pcrel_hi
| "fld f0, %0 \n\t"
<inline asm>:1:2: note: instantiated into assembly here
| fld f0, %pcrel_lo(.Lpcrel_hi0)(a0)
```

After transformations MachineFunction contains inline asm instructions
with
'.Lpcrel_hi0' symbol that is not defined in inline asm, but referenced.
```
... = AUIPC ...(riscv-pcrel-hi) @double_val, pre-instr-symbol <mcsymbol .Lpcrel_hi0>
INLINEASM &"fld f0, $0 \0A\09" ... target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi0>
```

So, when AsmParser processes 'fld', it has to create a new symbol as
'.Lpcrel_hi0' already exists but not known to be referenced in inline
asm.
AsmParser avoids conflicts by renaming referenced by 'fld' symbol with
'.Lpcrel_hi00' name which does not exist. Resulting erroneous asm
```
.Lpcrel_hi0:
auipc a0, %pcrel_hi(double_val)
#APP
fld ft0, %pcrel_lo(.Lpcrel_hi00)(a0)
```

This change adds symbols used in memory operands to the list of
referenced ones.

Godbolt link: https://godbolt.org/z/aqrrsWKoK -- on the left you can
find incorrect labels for the integrated-as and on the right an error
when compiling to the binary object.

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[test][RISCV] Precommit inline asm tests for #104925

[RISCV] Don't crash in RISCVMergeBaseOffset if INLINE_ASM uses address register in a non-memory constraint. (#100790)

If the register is used by a non-memory constraint we should disable the
fold.

[RISCV] Don't crash in RISCVMergeBaseOffset if INLINE_ASM uses address register in a non-memory constraint. (#100790)

If the register is used by a non-memory constraint we should disable the
fold. Otherwise, we may leave CommonOffset unassigned.

Fixes #100779.

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[RISCV] Teach RISCVMergeBaseOffset to handle inline asm (#78945)

For inline asm with memory operands, we can merge the offset into
the second operand of memory constraint operands.

Differential Rev

[RISCV] Teach RISCVMergeBaseOffset to handle inline asm (#78945)

For inline asm with memory operands, we can merge the offset into
the second operand of memory constraint operands.

Differential Revision: https://reviews.llvm.org/D158062

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[RISCV] Add tests for memory constraint A

We should not optimize it in D158062. This adds the test coverage.

And unneeded attributes `nonnull` and `inbounds` are removed.

Reviewed By: asb

Differe

[RISCV] Add tests for memory constraint A

We should not optimize it in D158062. This adds the test coverage.

And unneeded attributes `nonnull` and `inbounds` are removed.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D159530

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[RISCV] Fix inline asm error for block address (#66640)

After commit cedf2ea, `RISCVMergeBaseOffset` can handle `BlockAddress`
currently. But we didn't handle it in `PrintAsmMemoryOperand` so we
g

[RISCV] Fix inline asm error for block address (#66640)

After commit cedf2ea, `RISCVMergeBaseOffset` can handle `BlockAddress`
currently. But we didn't handle it in `PrintAsmMemoryOperand` so we
get `invalid operand in inline asm` error.

This patch fixes the error.

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Revert "[RISCV] Teach RISCVMergeBaseOffset to handle inline asm"

This reverts commit f281543a48905e58359c6b0f1b9c3b42bd67e315.

Sami Tolvanen reports that this breaks the Linux kernel's arch=RISCV
d

Revert "[RISCV] Teach RISCVMergeBaseOffset to handle inline asm"

This reverts commit f281543a48905e58359c6b0f1b9c3b42bd67e315.

Sami Tolvanen reports that this breaks the Linux kernel's arch=RISCV
defconfig.

Link: https://github.com/ClangBuiltLinux/linux/issues/1928

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[RISCV] Teach RISCVMergeBaseOffset to handle inline asm

For inline asm with memory operands, we can merge the offset into
the second operand of memory constraint operands.

Reviewed By: craig.topper

[RISCV] Teach RISCVMergeBaseOffset to handle inline asm

For inline asm with memory operands, we can merge the offset into
the second operand of memory constraint operands.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D158062

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[RISCV] Precommit test for D158062

Tests for callbr, multi-operands and multi-asm are added.

Reviewed By: wangpc, craig.topper

Differential Revision: https://reviews.llvm.org/D158149

[RISCV] Support global address as inline asm memory operand of `m`

In D146245, we have supported lowering inline asm `m` with offset
to `register+imm`, but we didn't handle the case that the offset

[RISCV] Support global address as inline asm memory operand of `m`

In D146245, we have supported lowering inline asm `m` with offset
to `register+imm`, but we didn't handle the case that the offset
is the low part of global address.

This patch will emit `%lo(g)` when `g` is a global address.

Fixes #64656

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D157839

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[RISCV][NFC] Move tests of inline asm memory constraints to separate file

We will need to check the output of medium code model.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org

[RISCV][NFC] Move tests of inline asm memory constraints to separate file

We will need to check the output of medium code model.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D157965

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