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Revision tags: llvmorg-21-init, llvmorg-19.1.7 |
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eeac0ffa |
| 10-Jan-2025 |
Nikita Popov <npopov@redhat.com> |
Revert "[MachineLICM] Use `RegisterClassInfo::getRegPressureSetLimit` (#119826)"
This reverts commit b4e17d4a314ed87ff6b40b4b05397d4b25b6636a.
This causes a large compile-time regression.
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b4e17d4a |
| 09-Jan-2025 |
Pengcheng Wang <wangpengcheng.pp@bytedance.com> |
[MachineLICM] Use `RegisterClassInfo::getRegPressureSetLimit` (#119826)
`RegisterClassInfo::getRegPressureSetLimit` is a wrapper of
`TargetRegisterInfo::getRegPressureSetLimit` with some logics to
a
[MachineLICM] Use `RegisterClassInfo::getRegPressureSetLimit` (#119826)
`RegisterClassInfo::getRegPressureSetLimit` is a wrapper of
`TargetRegisterInfo::getRegPressureSetLimit` with some logics to
adjust the limit by removing reserved registers.
It seems that we shouldn't use
`TargetRegisterInfo::getRegPressureSetLimit`
directly, just like the comment "This limit must be adjusted
dynamically for reserved registers" said.
Separate from https://github.com/llvm/llvm-project/pull/118787
show more ...
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Revision tags: llvmorg-19.1.6 |
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9afaf9c6 |
| 15-Dec-2024 |
Fangrui Song <i@maskray.me> |
[AMDGPU,test] Change llc -march= to -mtriple=
Follow-up to 806761a7629df268c8aed49657aeccffa6bca449
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Revision tags: llvmorg-19.1.5, llvmorg-19.1.4 |
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6548b635 |
| 09-Nov-2024 |
Shilei Tian <i@tianshilei.me> |
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
This reverts commit ca33649abe5fad93c57afef54e43ed9b3249cd86.
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ca33649a |
| 08-Nov-2024 |
Shilei Tian <i@tianshilei.me> |
Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
This reverts commit e215a1e27d84adad2635a52393621eb4fa439dc9 as it broke both
hip and openmp buildbots.
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e215a1e2 |
| 08-Nov-2024 |
Shilei Tian <i@tianshilei.me> |
[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)
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Revision tags: llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1 |
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6a1b1190 |
| 24-Jul-2024 |
Jessica Del <50999226+OutOfCache@users.noreply.github.com> |
[AMDGPU] Add intrinsics for atomic struct buffer loads (#100140)
Mark these intrinsics as atomic loads within LLVM to prevent hoisting
out of loops in cases where
the load is considered invariant.
[AMDGPU] Add intrinsics for atomic struct buffer loads (#100140)
Mark these intrinsics as atomic loads within LLVM to prevent hoisting
out of loops in cases where
the load is considered invariant.
Similar to https://github.com/llvm/llvm-project/pull/97707, but for
struct buffer loads.
show more ...
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