[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)

This allows folding of 64-bit operands if fit into 32-bit. Fixes
https://github.com/llvm/llvm-project/issues/67781

[AMDGPU] support 64-bit immediates in SIInstrInfo::FoldImmediate (#69260)

This is a part of https://github.com/llvm/llvm-project/issues/67781.
Until we select more 64-bit move immediates the impact

[AMDGPU] support 64-bit immediates in SIInstrInfo::FoldImmediate (#69260)

This is a part of https://github.com/llvm/llvm-project/issues/67781.
Until we select more 64-bit move immediates the impact is minimal.

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AMDGPU: Convert some assorted tests to opaque pointers

test: Don't depend on behavior of switch lower in one test. NFC

This is a preliminary change to update the test so that it does not
depend on how switch-case will be lowered. The following change wi

test: Don't depend on behavior of switch lower in one test. NFC

This is a preliminary change to update the test so that it does not
depend on how switch-case will be lowered. The following change will
lower switch-case more optimally that will make the test no longer
valid.

Reviewed by: arsenm

Differential Revision: https://reviews.llvm.org/D123606

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[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range

Currently the return address ABI registers s[30:31], which fall in the call
clobbered register range, are added a

[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range

Currently the return address ABI registers s[30:31], which fall in the call
clobbered register range, are added as a live-in on the function entry to
preserve its value when we have calls so that it gets saved and restored
around the calls.

But the DWARF unwind information (CFI) needs to track where the return address
resides in a frame and the above approach makes it difficult to track the
return address when the CFI information is emitted during the frame lowering,
due to the involvment of understanding the control flow.

This patch moves the return address ABI registers s[30:31] into callee saved
registers range and stops adding live-in for return address registers, so that
the CFI machinery will know where the return address resides when CSR
save/restore happen during the frame lowering.

And doing the above poses an issue that now the return instruction uses undefined
register `sgpr30_sgpr31`. This is resolved by hiding the return address register
use by the return instruction through the `SI_RETURN` pseudo instruction, which
doesn't take any input operands, until the `SI_RETURN` pseudo gets lowered to the
`S_SETPC_B64_return` during the `expandPostRAPseudo()`.

As an added benefit, this patch simplifies overall return instruction handling.

Note: The AMDGPU CFI changes are there only in the downstream code and another
version of this patch will be posted for review for the downstream code.

Reviewed By: arsenm, ronlieb

Differential Revision: https://reviews.llvm.org/D114652

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[AMDGPU] Ensure return address is save/restored if clobbered or when function has calls

This test is to make sure the return address registers, if clobbered in the
function or when the function has

[AMDGPU] Ensure return address is save/restored if clobbered or when function has calls

This test is to make sure the return address registers, if clobbered in the
function or when the function has calls, are save/restored irrespective of
whether the IPRA is enabled/disabled.

This test is found to be not save/restore the return address registers, when
clobbered in the function, with the corresponding downstream changes of D114652.

The test could not be reduced further as the register allocator needs enough
register pressure so that it allocates the return address registers as well.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D120922

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