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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2 |
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| #
5f94b0cb |
| 07-Oct-2024 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
AMDGPU: Try to reuse dest reg for s_add_i32 frame indexes (#111201)
Hack around the register scavenger doing the wrong thing.
It does not find the result register as available in the
case the fram
AMDGPU: Try to reuse dest reg for s_add_i32 frame indexes (#111201)
Hack around the register scavenger doing the wrong thing.
It does not find the result register as available in the
case the frame index add isn't also reading the dest register.
This is the quick fix for a regression where the scavenge would
create a broken spill of SGPR to memory. I believe this is still
broken for cases we cannot use the result register.
I'm confused about what position the scavenger iterator
is supposed to be in, and what RestoreAfter is for. The scavenger
is missing a full set of forward/backward APIs and there seems
to be an off by one somewhere.
show more ...
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Revision tags: llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4 |
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| #
8039886e |
| 22-Aug-2024 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
AMDGPU: Handle folding frame indexes into s_add_i32 (#101694)
This does not yet enable producing direct frame index
references in s_add_i32, only the lowering.
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Revision tags: llvmorg-19.1.0-rc3 |
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| #
ca409892 |
| 05-Aug-2024 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
AMDGPU: Permit more frame index operands in verifier (#101691)
Treat FI operands more like a register. When it gets materialized,
we will typically need to introduce a scavenged register anyway.
Add
AMDGPU: Permit more frame index operands in verifier (#101691)
Treat FI operands more like a register. When it gets materialized,
we will typically need to introduce a scavenged register anyway.
Add baseline tests for folding frame indexes into add/or.
show more ...
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