[RISCV] Support __builtin_cpu_is

We have defined `__riscv_cpu_model` variable in #101449. It contains
`mvendorid`, `marchid` and `mimpid` fields which are read via system
call `sys_riscv_hwprobe`.

[RISCV] Support __builtin_cpu_is

We have defined `__riscv_cpu_model` variable in #101449. It contains
`mvendorid`, `marchid` and `mimpid` fields which are read via system
call `sys_riscv_hwprobe`.

We can support `__builtin_cpu_is` via comparing values in compiler's
CPU definitions and `__riscv_cpu_model`.

This depends on #116202.

Reviewers: lenary, BeMg, kito-cheng, preames, lukel97

Reviewed By: lenary

Pull Request: https://github.com/llvm/llvm-project/pull/116231

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[RISCV] Add mvendorid/marchid/mimpid to CPU definitions (#116202)

We can get these information via `sys_riscv_hwprobe`.

This can be used to implement `__builtin_cpu_is`.

Revert "[RISCV] Add mvendorid/marchid/mimpid to CPU definitions (#116202)" chain

This reverts commit b36fcf4f493ad9d30455e178076d91be99f3a7d8.
This reverts commit c11b6b1b8af7454b35eef342162dc2cddf5

Revert "[RISCV] Add mvendorid/marchid/mimpid to CPU definitions (#116202)" chain

This reverts commit b36fcf4f493ad9d30455e178076d91be99f3a7d8.
This reverts commit c11b6b1b8af7454b35eef342162dc2cddf54b4de.
This reverts commit 775148f2367600f90d28684549865ee9ea2f11be.

multiple bot build breakages, e.g. https://lab.llvm.org/buildbot/#/builders/3/builds/8076

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[RISCV] Rename variable CPUModel to Model

The variable name can't be the same as the struct name or we will
have "error: declaration of ‘llvm::RISCV::CPUModel llvm::RISCV::CPUInfo::CPUModel’
changes

[RISCV] Rename variable CPUModel to Model

The variable name can't be the same as the struct name or we will
have "error: declaration of ‘llvm::RISCV::CPUModel llvm::RISCV::CPUInfo::CPUModel’
changes meaning of ‘CPUModel’ [-fpermissive]".

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[RISCV] Support __builtin_cpu_is

We have defined `__riscv_cpu_model` variable in #101449. It contains
`mvendorid`, `marchid` and `mimpid` fields which are read via system
call `sys_riscv_hwprobe`.

[RISCV] Support __builtin_cpu_is

We have defined `__riscv_cpu_model` variable in #101449. It contains
`mvendorid`, `marchid` and `mimpid` fields which are read via system
call `sys_riscv_hwprobe`.

We can support `__builtin_cpu_is` via comparing values in compiler's
CPU definitions and `__riscv_cpu_model`.

This depends on #116202.

Reviewers: lenary, BeMg, kito-cheng, preames, lukel97

Reviewed By: lenary

Pull Request: https://github.com/llvm/llvm-project/pull/116231

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[RISCV] Add mvendorid/marchid/mimpid to CPU definitions (#116202)

We can get these information via `sys_riscv_hwprobe`.

This can be used to implement `__builtin_cpu_is`.

[TargetParser] Remove unused includes (NFC) (#116929)

Identified with misc-include-cleaner.

[RISCV] Remove unused function (NFC)

/llvm-project/llvm/lib/TargetParser/RISCVTargetParser.cpp:148:1:
error: unused function 'getExtensionBitmask' [-Werror,-Wunused-function]
getExtensionBitmask(Str

[RISCV] Remove unused function (NFC)

/llvm-project/llvm/lib/TargetParser/RISCVTargetParser.cpp:148:1:
error: unused function 'getExtensionBitmask' [-Werror,-Wunused-function]
getExtensionBitmask(StringRef ExtName) {
^
1 error generated.

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[RISCV] Add groupid/bitmask for RISC-V extension (#94440)

Base on https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74.

This patch defines the groupid/bitmask in RISCVFeatures.td and generate

[RISCV] Add groupid/bitmask for RISC-V extension (#94440)

Base on https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74.

This patch defines the groupid/bitmask in RISCVFeatures.td and generates
the corresponding table in RISCVTargetParserDef.inc.

The groupid/bitmask of extensions provides an abstraction layer between
the compiler and runtime functions.

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[RISCV] Add -m[no-]scalar-strict-align and -m[no-]vector-strict-align. (#95024)

[RISCV] Split code that tablegen needs out of RISCVISAInfo. (#89684)

This introduces a new file, RISCVISAUtils.cpp and moves the rest of
RISCVISAInfo to the TargetParser library.

This will allow

[RISCV] Split code that tablegen needs out of RISCVISAInfo. (#89684)

This introduces a new file, RISCVISAUtils.cpp and moves the rest of
RISCVISAInfo to the TargetParser library.

This will allow us to generate part of RISCVISAInfo.cpp using tablegen.

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[RISCV] Move RISCVVType namespace to TargetParser (#83222)

Clang and some middle-end optimizations may need these helper
functions.

This can reduce some duplications.

[RISCV] Add getFeaturesForCPU function support (#83269)

This function parse the cpu and return it's supported
features placed in EnabledFeatures. It is same as the
one in X86TargetParser and also

[RISCV] Add getFeaturesForCPU function support (#83269)

This function parse the cpu and return it's supported
features placed in EnabledFeatures. It is same as the
one in X86TargetParser and also is used in IREE.

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[RISCV][Clang][TargetParser] Support getting feature unaligned-scalar-mem from mcpu. (#71513)

This patch reference ac1ffd3caca12c254e0b8c847aa8ce8e51b6cfbf to suppot
a soft coding way to identify w

[RISCV][Clang][TargetParser] Support getting feature unaligned-scalar-mem from mcpu. (#71513)

This patch reference ac1ffd3caca12c254e0b8c847aa8ce8e51b6cfbf to suppot
a soft coding way to identify whether a cpu has a feature
`unaligned-scalar-mem` by `RISCVProcessors.td`.
This patch does not provide test case since there is no risc-v cpu
support `unaligned-scalar-mem` in llvm upstream now.

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[RISCV] Don't store CPUKind in CPUInfo. NFC

This field is never used today. If you have a pointer to the row
you can find the CPUKind by subtracting the pointer from the start
of the array.

[RISCV] Remove INVALID from the list of CPUs in RISCVTargetParser. NFC

This value is never used outside and is only used as a sentinel
internally which we can solve with other means.

[RISCV] Remove or simplify some StringSwitches in RISCVTargetParser.cpp. NFC

We can iterate over the RISCVCPUInfo table instead of using a
separate StringSwitch.

[RISCV] Merge RISCV::parseCPUKind and RISCV::checkCPUKind.

Similar for RISCV::parseTuneCPU and RISCV::checkTuneCPUKind.

This makes the CPUKind enum no longer part of the API. It wasn't
providing mu

[RISCV] Merge RISCV::parseCPUKind and RISCV::checkCPUKind.

Similar for RISCV::parseTuneCPU and RISCV::checkTuneCPUKind.

This makes the CPUKind enum no longer part of the API. It wasn't
providing much value. It was only used to pass between the two
functions.

By removing it, we can remove a dependency on a tablegen generated
file from the RISCVTargetParser.h file. Then we can remove a
dependency from several CMakeLists.txt.

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[CodeGen][RISCV] Change Shadow Call Stack Register to X3

ShadowCallStack implementation uses s2 register on RISC-V, but that
choice is problematic for reasons described in:

https://lists.riscv.org/

[CodeGen][RISCV] Change Shadow Call Stack Register to X3

ShadowCallStack implementation uses s2 register on RISC-V, but that
choice is problematic for reasons described in:

https://lists.riscv.org/g/sig-toolchains/message/544,
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/370, and
https://github.com/google/android-riscv64/issues/72

The concern over the register choice was also brought up in
https://reviews.llvm.org/D84414.

https://reviews.llvm.org/D84414#2228666 said:

```
"If the register choice is the only concern about this work, then I think
we can probably land it as-is and fixup the register choice if we see
major drawbacks later. Yes, it's an ABI issue, but on the other hand the
shadow call stack is not a standard ABI anyway.""
```

Since we have now found a sufficient reason to fixup the register
choice, we should go ahead and update the implementation. We propose
using x3(gp) which is now the platform register in the RISC-V ABI.

Reviewed By: asb, hiraditya, mcgrathr, craig.topper

Differential Revision: https://reviews.llvm.org/D146463

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[RISCV] Remove getCPUFeaturesExceptStdExt.

This function was used to force +64bit or -64bit into the feature
string basd on -mcpu.

It's not entirely clear to me why this was needed. This informati

[RISCV] Remove getCPUFeaturesExceptStdExt.

This function was used to force +64bit or -64bit into the feature
string basd on -mcpu.

It's not entirely clear to me why this was needed. This informationo
is redundant with the triple. RISCVTargetInfo::initFeatureMap
independently recomputes it from the triple for the feature map.

It is ultimately needed in the backend, but that should be handled
by RISCVSubtarget processing the CPU name.

Differential Revision: https://reviews.llvm.org/D147978

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[RISCV] Replace RISCV -> RISC-V in comments. NFC

To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

[RISCV] Replace RISCV -> RISC-V in comments. NFC

To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

More patches will follow.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146449

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[RISCV] Reserve X18 by default for Android

Reserve X18 even when -fsanitize=shadow-call-stack is not enabled.

Based on: https://reviews.llvm.org/D143355

Reviewed by: asb, samitolvanen, phosek, Mas

[RISCV] Reserve X18 by default for Android

Reserve X18 even when -fsanitize=shadow-call-stack is not enabled.

Based on: https://reviews.llvm.org/D143355

Reviewed by: asb, samitolvanen, phosek, MaskRay

Differential Revision: https://reviews.llvm.org/D145999

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[RISCV] Default to -ffixed-x18 for Fuchsia

Fuchsia's ABI always reserves the x18 (s2) register for the
ShadowCallStack ABI, even when -fsanitize=shadow-call-stack is
not enabled.

Reviewed By: phose

[RISCV] Default to -ffixed-x18 for Fuchsia

Fuchsia's ABI always reserves the x18 (s2) register for the
ShadowCallStack ABI, even when -fsanitize=shadow-call-stack is
not enabled.

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D143355

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[RISCV] Remove Features from CPUInfo in RISCVTargetParser.

Instead of having separate feature bits, get information from march.
Invalid is now implied by empty march.
64-bit is now implied by march

[RISCV] Remove Features from CPUInfo in RISCVTargetParser.

Instead of having separate feature bits, get information from march.
Invalid is now implied by empty march.
64-bit is now implied by march starting with "rv64".

Reviewed By: fpetrogalli

Differential Revision: https://reviews.llvm.org/D142230

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[TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

Rework the change to prevent build failures. NFCI.

The failing code was submitted as
cf7a8305a2b4ddfd299c748136cb9a2960ef7089 and

[TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

Rework the change to prevent build failures. NFCI.

The failing code was submitted as
cf7a8305a2b4ddfd299c748136cb9a2960ef7089 and reverted via
8bd65e535fb33bc48805bafed8217b16a853e158.

The rework in this new commit prevents failures like the following:

FAILED: tools/clang/lib/Basic/CMakeFiles/obj.clangBasic.dir/Targets/RISCV.cpp.o
/usr/bin/c++ [bunch of non interesting stuff] -c <path-to>/llvm-project/clang/lib/Basic/Targets/RISCV.cpp
In file included from <path-to>/llvm-project/clang/lib/Basic/Targets/RISCV.cpp:19:
<path-to>/llvm-project/llvm/include/llvm/TargetParser/RISCVTargetParser.h:29:10: fatal error: llvm/TargetParser/RISCVTargetParserDef.inc: No such file or directory
29 | #include "llvm/TargetParser/RISCVTargetParserDef.inc"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

These failures happen because the library LLVMTargetParser depends on
RISCVTargetParserTableGen, which is a tablegen target that generates
the list of CPUs in
llvm/TargetParser/RISCVTargetParserDef.inc. This *.inc file is
included by the public header file
llvm/TargetParser/RISCVTargetParser.h.

The header file llvm/TargetParser/RISCVTargetParser.h is also used in
components (clangDriver and clangBasic) that link into
LLVMTargetParser, but on some configurations such components might end
up being built before TargetParser is ready.

The fix is to make sure that clangDriver and clangBasic depend on the
tablegen target RISCVTargetParserTableGen, which generates the .inc
file whether or not LLVMTargetParser is ready.

WRT the original patch at https://reviews.llvm.org/D137517, this
commit is just adding RISCVTargetParserTableGen in the DEPENDS list of
clangDriver and clangBasic.

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