[SPIRV] Add vector reduction instructions (#82786)

This PR is to add vector reduction instructions according to
https://llvm.org/docs/GlobalISel/GenericOpcode.html#vector-reduction-operations
and

[SPIRV] Add vector reduction instructions (#82786)

This PR is to add vector reduction instructions according to
https://llvm.org/docs/GlobalISel/GenericOpcode.html#vector-reduction-operations
and widen in such a way a range of successful supported conversions,
covering new cases of vector reduction instructions which IRTranslator
is unable to resolve.

By legalizing vector reduction instructions we introduce a new
instruction patterns that should be addressed, including patterns that
are delegated to pre-legalize step. To address this problem, a new pass
is added that is to bring newly generated instructions after
legalization to an aspect required by instruction selection.

Expected overheads for existing cases is minimal, because a new pass is
working only with newly introduced instructions, otherwise it's just a
additional code traverse without any actions.

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[SPIR-V]: add SPIR-V extension: SPV_INTEL_variable_length_array (#83002)

This PR adds SPIR-V extension SPV_INTEL_variable_length_array that
allows to allocate local arrays whose number of elements

[SPIR-V]: add SPIR-V extension: SPV_INTEL_variable_length_array (#83002)

This PR adds SPIR-V extension SPV_INTEL_variable_length_array that
allows to allocate local arrays whose number of elements is unknown at
compile time:
* add a new SPIR-V internal intrinsic:int_spv_alloca_array
* legalize G_STACKSAVE and G_STACKRESTORE
* implement allocation of arrays (previously getArraySize() of
AllocaInst was not used)
* add tests

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Add support for the 'freeze' instruction (#82979)

This PR is to add support for the 'freeze' instruction:
https://llvm.org/docs/LangRef.html#freeze-instruction

There is no way to implement `free

Add support for the 'freeze' instruction (#82979)

This PR is to add support for the 'freeze' instruction:
https://llvm.org/docs/LangRef.html#freeze-instruction

There is no way to implement `freeze` correctly without support on
SPIR-V standard side, but we may at least address a simple (static) case
when undef/poison value presence is obvious. The main benefit of even
incomplete `freeze` support is preventing of translation from crashing
due to lack of support on legalization and instruction selection steps.

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Add support for the SPV_INTEL_usm_storage_classes extension (#82247)

Add support for the SPV_INTEL_usm_storage_classes extension:
*
https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-ex

Add support for the SPV_INTEL_usm_storage_classes extension (#82247)

Add support for the SPV_INTEL_usm_storage_classes extension:
*
https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_usm_storage_classes.asciidoc

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Add support for atomic instruction on floating-point numbers (#81683)

This PR adds support for atomic instruction on floating-point numbers:

* SPV_EXT_shader_atomic_float_add
* SPV_EXT_shader_at

Add support for atomic instruction on floating-point numbers (#81683)

This PR adds support for atomic instruction on floating-point numbers:

* SPV_EXT_shader_atomic_float_add
* SPV_EXT_shader_atomic_float_min_max
* SPV_EXT_shader_atomic_float16_add

and fixes asm printer output for half floating-type.

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add support for the SPV_KHR_linkonce_odr extension (#81512)

This PR adds support for the SPV_KHR_linkonce_odr extension and modifies
existing negative test with a positive check for the extension a

add support for the SPV_KHR_linkonce_odr extension (#81512)

This PR adds support for the SPV_KHR_linkonce_odr extension and modifies
existing negative test with a positive check for the extension and
proper linkage type in case when the extension is enabled.

SPV_KHR_linkonce_odr adds a "LinkOnceODR" linkage type, allowing proper
translation of, for example, C++ templates classes merging during
linking from different modules and supporting any other cases when a
global variable/function must be merged with equivalent global
variable(s)/function(s) from other modules during the linking process.

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Add support for SPIR-V extension: SPV_INTEL_function_pointers (#80759)

This PR adds initial support for "SPV_INTEL_function_pointers" SPIR-V
extension:
https://github.com/intel/llvm/blob/sycl/sycl

Add support for SPIR-V extension: SPV_INTEL_function_pointers (#80759)

This PR adds initial support for "SPV_INTEL_function_pointers" SPIR-V
extension:
https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_function_pointers.asciidoc

The goal of the extension is to support indirect function calls and
translation of function pointers into SPIR-V.

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generate a name of an unnamed global variable for Instruction Selection (#78293)

The goal of this PR is to fix the issue of global unnamed variables
causing SPIR-V Backend code generation to crash:

generate a name of an unnamed global variable for Instruction Selection (#78293)

The goal of this PR is to fix the issue of global unnamed variables
causing SPIR-V Backend code generation to crash:
https://github.com/llvm/llvm-project/issues/78278

The reason for the crash is that GlobalValue's getGlobalIdentifier()
would fail for unnamed global variable when trying to access the first
character of the name (see lib/IR/Globals.cpp:150). This leads to assert
in Debug and undefined behaviour in Release builds.

The proposed fix generates a name of an unnamed global variable as
__unnamed_<unsigned number>, in a style of similar existing LLVM
implementation (see lib/IR/Mangler.cpp:131). A new class member variable
is added into `SPIRVInstructionSelector` class to keep track of the
number we give to anonymous global values to generate the same name
every time when this is needed.

The patch adds a new LIT test with the smallest implementation of
reproducer ll code.

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[SPIRV] Fix SPV_KHR_expect_assume support (#67793)

Since efe0e10718 changes in tests are required. Need to add extension to
Extensions list
and command line to enable use of the extension for test

[SPIRV] Fix SPV_KHR_expect_assume support (#67793)

Since efe0e10718 changes in tests are required. Need to add extension to
Extensions list
and command line to enable use of the extension for test runs.

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[SPIRV] Implement log10 for logical SPIR-V (#66921)

There is no log10 instruction in the GLSL Extended Instruction Set so to
implement the HLSL log10 intrinsic when targeting Vulkan this change
ad

[SPIRV] Implement log10 for logical SPIR-V (#66921)

There is no log10 instruction in the GLSL Extended Instruction Set so to
implement the HLSL log10 intrinsic when targeting Vulkan this change
adds the logic to derive the result using the following formula:
```
log10(x) = log2(x) * (1 / log2(10))
= log2(x) * 0.30103
```

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[NFC][SPIRV] fix missing uppercase for var name (#67438)

Typo fix.

Signed-off-by: Nathan Gauër <brioche@google.com>

[SPIRV] Add OpAccessChain instruction support (#66253)

This commit adds 2 new instructions in the selector:
- OpAccessChain
- OpInBoundsAccessChain.

The choice between the two relies on the `

[SPIRV] Add OpAccessChain instruction support (#66253)

This commit adds 2 new instructions in the selector:
- OpAccessChain
- OpInBoundsAccessChain.

The choice between the two relies on the `inbounds` marker.

Those instruction are not used for OpenCL, to maintain the same
behavior as previously. They are only added when building for logical
SPIR-V, as it doesn't support the pointer equivalent.

Because logical SPIR-V doesn't support pointer cast either, the
assign_ptr_type intrinsic need to be generated so OpAccessChain gets
lowered with the correct pointer type, instead of i8*.

Fixes #66107

---------

Signed-off-by: Nathan Gauër <brioche@google.com>

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[SPIRV] Implement support for SPV_KHR_expect_assume (#66217)

Adds new extension SPV_KHR_expect_assume, new capability
ExpectAssumeKHR as well as the new instructions:
* OpExpectKHR
* OpAssume

[SPIRV] Implement support for SPV_KHR_expect_assume (#66217)

Adds new extension SPV_KHR_expect_assume, new capability
ExpectAssumeKHR as well as the new instructions:
* OpExpectKHR
* OpAssumeTrueKHR

These are lowered from respectively llvm.expect.<ty> and llvm.assume
intrinsics.

Previously https://reviews.llvm.org/D157696

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[SPIR-V] Remove -opaque-pointers=0 from LITs, fixes for opaque pointers support

Differential Revision: https://reviews.llvm.org/D156049

[GlobalISel] convergent intrinsics

Introduced the convergent equivalent of the existing G_INTRINSIC opcodes:

- G_INTRINSIC_CONVERGENT
- G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS

Out of the targets tha

[GlobalISel] convergent intrinsics

Introduced the convergent equivalent of the existing G_INTRINSIC opcodes:

- G_INTRINSIC_CONVERGENT
- G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS

Out of the targets that currently have some support for GlobalISel, the patch
assumes that the convergent intrinsics only relevant to SPIRV and AMDGPU.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D154766

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Restore "[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR"

Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic
ID is the first non-def operan

Restore "[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR"

Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic
ID is the first non-def operand to the instruction. These are now represented as
a subclass of GenericMachineInstr, and the method MachineInstr::getIntrinsicID()
is now moved to this subclass GIntrinsic.

Some target-defined instructions behave like GMIR intrinsics, and have an
Intrinsic::ID operand. But they should not be recognized as generic intrinsics,
and should not use GIntrinsic::getIntrinsicID(). Separated these out by
introducing a new AMDGPU::getIntrinsicID().

Reviewed By: arsenm, Pierre-vh

Differential Revision: https://reviews.llvm.org/D155556

This restores commit baa3386edb11a2f9bcadda8cf58d56f3707c39fa.
Originally reverted in d0f7850b01cf17e50a4f4b00e3b84dded94df6b8.

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Revert "[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR"

This reverts commit baa3386edb11a2f9bcadda8cf58d56f3707c39fa.

The changes did not cover all occurrences of th

Revert "[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR"

This reverts commit baa3386edb11a2f9bcadda8cf58d56f3707c39fa.

The changes did not cover all occurrences of the deteleted function
MachineInstr::getIntrinsicID().

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[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR

Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic
ID is the first non-def operand to the i

[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR

Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic
ID is the first non-def operand to the instruction. These are now represented as
a subclass of GenericMachineInstr, and the method MachineInstr::getIntrinsicID()
is now moved to this subclass GIntrinsic.

Some target-defined instructions behave like GMIR intrinsics, and have an
Intrinsic::ID operand. But they should not be recognized as generic intrinsics,
and should not use GIntrinsic::getIntrinsicID(). Separated these out by
introducing a new AMDGPU::getIntrinsicID().

Reviewed By: arsenm, Pierre-vh

Differential Revision: https://reviews.llvm.org/D155556

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[SPIRV] Fix CoverageInfo after D153758

[AMDGPU] Use GlobalISel MatchTable Combiner Backend

Use the new matchtable-based combiner backend for all AMDGPU combiners.
This drop-in from the user's perspective; there are no test changes, the n

[AMDGPU] Use GlobalISel MatchTable Combiner Backend

Use the new matchtable-based combiner backend for all AMDGPU combiners.
This drop-in from the user's perspective; there are no test changes, the new combiner behaves exactly like the old one.

Depends on D153757

NOTE: This would land iff D153757 (RFC) lands too.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D153758

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[GlobalISel] Generalize `InstructionSelector` Match Tables

Makes `InstructionSelector.h`/`InstructionSelectorImpl.h` generic so the match tables can also be used for the combiner.

Some notes:
- Co

[GlobalISel] Generalize `InstructionSelector` Match Tables

Makes `InstructionSelector.h`/`InstructionSelectorImpl.h` generic so the match tables can also be used for the combiner.

Some notes:
- Coverage was made an optional parameter of `executeMatchTable`, combines won't use it for now.
- `GIPFP_` -> `GICXXPred_` so it's more generic. Those are just C++ predicates and aren't PatFrag-specific.
- Pass the MatcherState directly to testMIPredicate_MI, the combiner will need it.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D153755

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[SPIR-V] Promote arbitrary width ints to regular width

After this patch all arbitrary size integers (smaller than 64 bits) in
LLVM IR will be promoted to regular size type in SPIR-V (OpTypeInt
8/16/

[SPIR-V] Promote arbitrary width ints to regular width

After this patch all arbitrary size integers (smaller than 64 bits) in
LLVM IR will be promoted to regular size type in SPIR-V (OpTypeInt
8/16/32/64).

Differential Revision: https://reviews.llvm.org/D145137

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[SPIR-V] Fix llvm deprecated warnings

Fixes warnings related to getAllOnesValue and isNullValue being
deprecated.

Differential Revision: https://reviews.llvm.org/D145709

[SPIR-V] Emit spv_undef intrinsic for aggregate undef operands

This change adds a new spv_undef intrinsic which is emitted in place of
aggregate undef operands and later selected to single OpUndef S

[SPIR-V] Emit spv_undef intrinsic for aggregate undef operands

This change adds a new spv_undef intrinsic which is emitted in place of
aggregate undef operands and later selected to single OpUndef SPIR-V
instruction. The behavior matches that of Khronos SPIR-V Translator and
should support nested aggregates.

Differential Revision: https://reviews.llvm.org/D143107

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[SPIRV] support builtin types and ExtInsts selection

The patch adds the support of OpenCL and SPIR-V built-in types. It also
implements ExtInst selection and adds spv_unreachable and spv_alloca
intr

[SPIRV] support builtin types and ExtInsts selection

The patch adds the support of OpenCL and SPIR-V built-in types. It also
implements ExtInst selection and adds spv_unreachable and spv_alloca
intrinsics which improve the generation of the corresponding SPIR-V code.
Five LIT tests are included to demonstrate the improvement.

Differential Revision: https://reviews.llvm.org/D132648

Co-authored-by: Aleksandr Bezzubikov <zuban32s@gmail.com>
Co-authored-by: Michal Paszkowski <michal.paszkowski@outlook.com>
Co-authored-by: Andrey Tretyakov <andrey1.tretyakov@intel.com>
Co-authored-by: Konrad Trifunovic <konrad.trifunovic@intel.com>

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