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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2 |
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| #
cc761a7c |
| 13-Mar-2024 |
Zaara Syeda <syzaara@ca.ibm.com> |
[PowerPC][NFC] Rename ADDItocL to match the 64-bit naming convention (#85099)
In preparation of adding a similar instruction for large code model on
AIX for 32-bit, rename the exisitng ADDItocL 64-
[PowerPC][NFC] Rename ADDItocL to match the 64-bit naming convention (#85099)
In preparation of adding a similar instruction for large code model on
AIX for 32-bit, rename the exisitng ADDItocL 64-instruction to ADDItocL8
to match the naming convention of other instructions with 32-bit and
64-bit variants.
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Revision tags: llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init |
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ea8b95d0 |
| 07-Dec-2023 |
Stefan Pintilie <stefanp@ca.ibm.com> |
[PowerPC] Add a set of extended mnemonics that are missing from Power 10. (#73003)
This patch adds the majority of the missing extended mnemonics that were
introduced in Power 10.
The only exten
[PowerPC] Add a set of extended mnemonics that are missing from Power 10. (#73003)
This patch adds the majority of the missing extended mnemonics that were
introduced in Power 10.
The only extended mnemonics that were not added are related to the plq
and pstq instructions. These will be added in a separate patch as the
instructions themselves would also have to be added.
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Revision tags: llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4 |
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| #
b4747390 |
| 24-Feb-2023 |
Stefan Pintilie <stefanp@ca.ibm.com> |
[PowerPC] Add Binary Coded Decimal Assist Instructions
This patch adds three instructions for Binary Coded Decimal (BCD).
They are: cdtbcd, cbcdtd, addg6s.
Reviewed By: amyk
Differential Revision:
[PowerPC] Add Binary Coded Decimal Assist Instructions
This patch adds three instructions for Binary Coded Decimal (BCD).
They are: cdtbcd, cbcdtd, addg6s.
Reviewed By: amyk
Differential Revision: https://reviews.llvm.org/D144068
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Revision tags: llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7 |
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bfde3bdd |
| 20-Dec-2022 |
Lei Huang <lei@ca.ibm.com> |
[PowerPC][NFC] Update p10 scheduler
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Revision tags: llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3 |
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0d253bbd |
| 14-Oct-2022 |
Nemanja Ivanovic <nemanja.i.ibm@gmail.com> |
[PowerPC] Change CRNOT to a code gen single operand instruction
Inputs to crnor can come from operands with chains so
if it is being used simply to negate such an operand,
the repeated input cannot
[PowerPC] Change CRNOT to a code gen single operand instruction
Inputs to crnor can come from operands with chains so
if it is being used simply to negate such an operand,
the repeated input cannot be CSE'd. This patch just
adds a code-gen only instruction for this that takes
a single input and duplicates it in the encoding of
the underlying crnor.
Differential revision: https://reviews.llvm.org/D133577
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Revision tags: working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4 |
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| #
c35ca3a1 |
| 19-May-2022 |
Amy Kwan <amy.kwan1@ibm.com> |
[PowerPC] Implement XL compat __fnabs and __fnabss builtins.
This patch implements the following floating point negative absolute value
builtins that required for compatibility with the XL compiler:
[PowerPC] Implement XL compat __fnabs and __fnabss builtins.
This patch implements the following floating point negative absolute value
builtins that required for compatibility with the XL compiler:
```
double __fnabs(double);
float __fnabss(float);
```
These builtins will emit :
- fnabs on PWR6 and below, or if VSX is disabled.
- xsnabsdp on PWR7 and above, if VSX is enabled.
Differential Revision: https://reviews.llvm.org/D125506
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Revision tags: llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2 |
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| #
e3c2694d |
| 06-Dec-2021 |
Qiu Chaofan <qiucofan@cn.ibm.com> |
[PowerPC] Implement general back2back fusion
Implement 'back-to-back' FX fusion according to Power10 User Manual
'19.1.5.4 Fusion', not enabled by default.
Reviewed By: nemanjai
Differential Revis
[PowerPC] Implement general back2back fusion
Implement 'back-to-back' FX fusion according to Power10 User Manual
'19.1.5.4 Fusion', not enabled by default.
Reviewed By: nemanjai
Differential Revision: https://reviews.llvm.org/D114345
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