[MIPS GlobalISel] Select MSA vector generic and builtin fabs

selectImpl is able to select G_FABS when we set bank for vector
operands to fprb. Add detailed tests.
Note: G_FABS is generated from llvm

[MIPS GlobalISel] Select MSA vector generic and builtin fabs

selectImpl is able to select G_FABS when we set bank for vector
operands to fprb. Add detailed tests.
Note: G_FABS is generated from llvm-ir intrinsics llvm.fabs.*,
and at the moment MIPS is not able to generate this intrinsic for
vector type (some targets generate vector llvm.fabs.* from calls
to a builtin function).
We can handle fabs using __builtin_msa_fmax_a_<format> and passing
same vector as both arguments. __builtin_msa_fmax_a_<format> will
be directly selected into FMAX_A_<format> in legalizeIntrinsic.

Differential Revision: https://reviews.llvm.org/D69346

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[MIPS GlobalISel] MSA vector generic and builtin fadd, fsub, fmul, fdiv

Select vector G_FADD, G_FSUB, G_FMUL and G_FDIV for MIPS32 with MSA. We
have to set bank for vector operands to fprb and selec

[MIPS GlobalISel] MSA vector generic and builtin fadd, fsub, fmul, fdiv

Select vector G_FADD, G_FSUB, G_FMUL and G_FDIV for MIPS32 with MSA. We
have to set bank for vector operands to fprb and selectImpl will do the
rest. __builtin_msa_fadd_<format>, __builtin_msa_fsub_<format>,
__builtin_msa_fmul_<format> and __builtin_msa_fdiv_<format> will be
transformed into G_FADD, G_FSUB, G_FMUL and G_FDIV in legalizeIntrinsic
respectively and selected in the same way.

Differential Revision: https://reviews.llvm.org/D69340

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[MIPS GlobalISel] MSA vector generic and builtin sdiv, srem, udiv, urem

Select vector G_SDIV, G_SREM, G_UDIV and G_UREM for MIPS32 with MSA. We
have to set bank for vector operands to fprb and selec

[MIPS GlobalISel] MSA vector generic and builtin sdiv, srem, udiv, urem

Select vector G_SDIV, G_SREM, G_UDIV and G_UREM for MIPS32 with MSA. We
have to set bank for vector operands to fprb and selectImpl will do the
rest. __builtin_msa_div_s_<format>, __builtin_msa_mod_s_<format>,
__builtin_msa_div_u_<format> and __builtin_msa_mod_u_<format> will be
transformed into G_SDIV, G_SREM, G_UDIV and G_UREM in legalizeIntrinsic
respectively and selected in the same way.

Differential Revision: https://reviews.llvm.org/D69333

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[MIPS GlobalISel] Select MSA vector generic and builtin mul

Select vector G_MUL for MIPS32 with MSA. We have to set bank
for vector operands to fprb and selectImpl will do the rest.
Manual selection

[MIPS GlobalISel] Select MSA vector generic and builtin mul

Select vector G_MUL for MIPS32 with MSA. We have to set bank
for vector operands to fprb and selectImpl will do the rest.
Manual selection of G_MUL is now done for gprb only.
__builtin_msa_mulv_<format> will be transformed into G_MUL
in legalizeIntrinsic and selected in the same way.

Differential Revision: https://reviews.llvm.org/D69310

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[MIPS GlobalISel] Select MSA vector generic and builtin sub

Select vector G_SUB for MIPS32 with MSA. We have to set bank
for vector operands to fprb and selectImpl will do the rest.
__builtin_msa_su

[MIPS GlobalISel] Select MSA vector generic and builtin sub

Select vector G_SUB for MIPS32 with MSA. We have to set bank
for vector operands to fprb and selectImpl will do the rest.
__builtin_msa_subv_<format> will be transformed into G_SUB
in legalizeIntrinsic and selected in the same way.
__builtin_msa_subvi_<format> will be directly selected into
SUBVI_<format> in legalizeIntrinsic.

Differential Revision: https://reviews.llvm.org/D69306

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[MIPS GlobalISel] Select MSA vector generic and builtin add

Select vector G_ADD for MIPS32 with MSA. We have to set bank
for vector operands to fprb and selectImpl will do the rest.
__builtin_msa_ad

[MIPS GlobalISel] Select MSA vector generic and builtin add

Select vector G_ADD for MIPS32 with MSA. We have to set bank
for vector operands to fprb and selectImpl will do the rest.
__builtin_msa_addv_<format> will be transformed into G_ADD
in legalizeIntrinsic and selected in the same way.
__builtin_msa_addvi_<format> will be directly selected into
ADDVI_<format> in legalizeIntrinsic. MIR tests for it have
unnecessary additional copies. Capture current state of tests
with run-pass=legalizer with a test in test/CodeGen/MIR/Mips.

Differential Revision: https://reviews.llvm.org/D68984

llvm-svn: 375501

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[MIPS GlobalISel] Add MSA registers to fprb. Select vector load, store

Add vector MSA register classes to fprb, they are 128 bit wide.
MSA instructions use the same registers for both integer and fl

[MIPS GlobalISel] Add MSA registers to fprb. Select vector load, store

Add vector MSA register classes to fprb, they are 128 bit wide.
MSA instructions use the same registers for both integer and floating
point operations. Therefore we only need to check for vector element
size during legalization or instruction selection.

Add helper function in MipsLegalizerInfo and switch to legalIf
LegalizeRuleSet to keep legalization rules compact since they depend
on MipsSubtarget and presence of MSA.
fprb is assigned to all vector operands.
Move selectLoadStoreOpCode to MipsInstructionSelector in order to
reduce number of arguments.

Differential Revision: https://reviews.llvm.org/D68867

llvm-svn: 374872

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[MIPS GlobalISel] Refactor MipsRegisterBankInfo [NFC]

Check if size of operand LLT matches sizes of available register banks
before inspecting the opcode in order to reduce number of checks.
Factor

[MIPS GlobalISel] Refactor MipsRegisterBankInfo [NFC]

Check if size of operand LLT matches sizes of available register banks
before inspecting the opcode in order to reduce number of checks.
Factor commonly used pieces of code into functions.

Differential Revision: https://reviews.llvm.org/D68866

llvm-svn: 374870

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[MIPS GlobalISel] VarArg argument lowering, select G_VASTART and vacopy

CC_Mips doesn't accept vararg functions for O32, so we have to explicitly
use CC_Mips_FixedArg.
For lowerCall we now properly

[MIPS GlobalISel] VarArg argument lowering, select G_VASTART and vacopy

CC_Mips doesn't accept vararg functions for O32, so we have to explicitly
use CC_Mips_FixedArg.
For lowerCall we now properly figure out whether callee function is vararg
or not, this has no effect for O32 since we always use CC_Mips_FixedArg.
For lower formal arguments we need to copy arguments in register to stack
and save pointer to start for argument list into MipsMachineFunction
object so that G_VASTART could use it during instruction select.
For vacopy we need to copy content from one vreg to another,
load and store are used for that purpose.

Differential Revision: https://reviews.llvm.org/D67756

llvm-svn: 372555

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[MIPS GlobalISel] Select indirect branch

Select G_BRINDIRECT for MIPS32.

Differential Revision: https://reviews.llvm.org/D67441

llvm-svn: 371730

[MIPS GlobalISel] Select G_IMPLICIT_DEF

G_IMPLICIT_DEF is used for both integer and floating point implicit-def.
Handle G_IMPLICIT_DEF as ambiguous opcode in MipsRegisterBankInfo.
Select G_IMPLICIT_

[MIPS GlobalISel] Select G_IMPLICIT_DEF

G_IMPLICIT_DEF is used for both integer and floating point implicit-def.
Handle G_IMPLICIT_DEF as ambiguous opcode in MipsRegisterBankInfo.
Select G_IMPLICIT_DEF for MIPS32.

Differential Revision: https://reviews.llvm.org/D67439

llvm-svn: 371727

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[MIPS GlobalISel] Select jump_table and brjt

G_JUMP_TABLE and G_BRJT appear from translation of switch statement.
Select these two instructions for MIPS32, both pic and non-pic.

Differential Revisi

[MIPS GlobalISel] Select jump_table and brjt

G_JUMP_TABLE and G_BRJT appear from translation of switch statement.
Select these two instructions for MIPS32, both pic and non-pic.

Differential Revision: https://reviews.llvm.org/D65861

llvm-svn: 368274

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Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC

llvm-svn: 367633

[MIPS GlobalISel] Select inttoptr and ptrtoint

Select G_INTTOPTR and G_PTRTOINT for MIPS32.

Differential Revision: https://reviews.llvm.org/D65217

llvm-svn: 367104

[MIPS GlobalISel] Skip copies in addUseDef and addDefUses

Skip copies between virtual registers during search for UseDefs
and DefUses.
Since each operand has one def search for UseDefs is straightfo

[MIPS GlobalISel] Skip copies in addUseDef and addDefUses

Skip copies between virtual registers during search for UseDefs
and DefUses.
Since each operand has one def search for UseDefs is straightforward.
But since operand can have many uses, we have to check all uses of
each copy we traverse during search for DefUses.

Differential Revision: https://reviews.llvm.org/D64486

llvm-svn: 365744

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[MIPS GlobalISel] RegBankSelect for chains of ambiguous instructions

When one of the uses/defs of ambiguous instruction is also ambiguous
visit it recursively and search its uses/defs for instructio

[MIPS GlobalISel] RegBankSelect for chains of ambiguous instructions

When one of the uses/defs of ambiguous instruction is also ambiguous
visit it recursively and search its uses/defs for instruction with
only one mapping available.
When all instruction in a chain are ambiguous arbitrary mapping can
be selected. For s64 operands in ambiguous chain fprb is selected since
it results in less instructions then having to narrow scalar s64 to s32.
For s32 both gprb and fprb result in same number of instructions and
gprb is selected like a general purpose option.

At the moment we always avoid cross register bank copies.
TODO: Implement a model for costs calculations of different mappings
on same instruction and cross bank copies. Allow cross bank copies
when appropriate according to cost model.

Differential Revision: https://reviews.llvm.org/D64485

llvm-svn: 365743

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[MIPS GlobalISel] Register bank select for G_PHI. Select i64 phi

Select gprb or fprb when def/use register operand of G_PHI is
used/defined by either:
copy to/from physical register or
instruction

[MIPS GlobalISel] Register bank select for G_PHI. Select i64 phi

Select gprb or fprb when def/use register operand of G_PHI is
used/defined by either:
copy to/from physical register or
instruction with only one mapping available for that use/def operand.

Integer s64 phi is handled with narrowScalar when mapping is applied,
produced artifacts are combined away. Manually set gprb to all register
operands of instructions created during narrowScalar.

Differential Revision: https://reviews.llvm.org/D64351

llvm-svn: 365494

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[MIPS GlobalISel] Regbanks for G_SELECT. Select i64, f32 and f64 select

Select gprb or fprb when def/use register operand of G_SELECT is
used/defined by either:
copy to/from physical register or
i

[MIPS GlobalISel] Regbanks for G_SELECT. Select i64, f32 and f64 select

Select gprb or fprb when def/use register operand of G_SELECT is
used/defined by either:
copy to/from physical register or
instruction with only one mapping available for that use/def operand.

Integer s64 select is handled with narrowScalar when mapping is applied,
produced artifacts are combined away. Manually set gprb to all register
operands of instructions created during narrowScalar.

For selection of floating point s32 or s64 select it is enough to set
fprb of appropriate size and selectImpl will do the rest.

Differential Revision: https://reviews.llvm.org/D64350

llvm-svn: 365492

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[MIPS GlobalISel] Register bank select for G_LOAD. Select i64 load

Select gprb or fprb when loaded value is used by either:
copy to physical register or
instruction with only one mapping available

[MIPS GlobalISel] Register bank select for G_LOAD. Select i64 load

Select gprb or fprb when loaded value is used by either:
copy to physical register or
instruction with only one mapping available for that use operand.

Load of integer s64 is handled with narrowScalar when mapping is applied,
produced artifacts are combined away. Manually set gprb to all register
operands of instructions created during narrowScalar.

Differential Revision: https://reviews.llvm.org/D64269

llvm-svn: 365323

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[MIPS GlobalISel] Register bank select for G_STORE. Select i64 store

Select gprb or fprb when stored value is defined by either:
copy from physical register or
instruction with only one mapping av

[MIPS GlobalISel] Register bank select for G_STORE. Select i64 store

Select gprb or fprb when stored value is defined by either:
copy from physical register or
instruction with only one mapping available for that def operand.

Store of integer s64 is handled with narrowScalar when mapping is applied,
produced artifacts are combined away. Manually set gprb to all register
operands of instructions created during narrowScalar.

Differential Revision: https://reviews.llvm.org/D64268

llvm-svn: 365322

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[MIPS GlobalISel] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds after D63541

llvm-svn: 364003

[MIPS GlobalISel] Select integer to floating point conversions

Select G_SITOFP and G_UITOFP for MIPS32.

Differential Revision: https://reviews.llvm.org/D63542

llvm-svn: 363912

[MIPS GlobalISel] Select floating point to integer conversions

Select G_FPTOSI and G_FPTOUI for MIPS32.

Differential Revision: https://reviews.llvm.org/D63541

llvm-svn: 363911

[MIPS GlobalISel] Select sqrt

Select G_FSQRT for MIPS32.

Differential Revision: https://reviews.llvm.org/D62905

llvm-svn: 362692

[MIPS GlobalISel] Select fabs

Select G_FABS for MIPS32.

Differential Revision: https://reviews.llvm.org/D62903

llvm-svn: 362690