xref: /llvm-project/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp (revision dbb6d01d340f5fecd0591f2ef25acb043bd6957b) 
1 //===- MipsRegisterBankInfo.cpp ---------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the RegisterBankInfo class for Mips.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsRegisterBankInfo.h"
14 #include "MipsInstrInfo.h"
15 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
16 #include "llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h"
17 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 
20 #define GET_TARGET_REGBANK_IMPL
21 
22 #include "MipsGenRegisterBank.inc"
23 
24 namespace llvm {
25 namespace Mips {
26 enum PartialMappingIdx {
27   PMI_GPR,
28   PMI_SPR,
29   PMI_DPR,
30   PMI_Min = PMI_GPR,
31 };
32 
33 RegisterBankInfo::PartialMapping PartMappings[]{
34     {0, 32, GPRBRegBank},
35     {0, 32, FPRBRegBank},
36     {0, 64, FPRBRegBank}
37 };
38 
39 enum ValueMappingIdx {
40     InvalidIdx = 0,
41     GPRIdx = 1,
42     SPRIdx = 4,
43     DPRIdx = 7
44 };
45 
46 RegisterBankInfo::ValueMapping ValueMappings[] = {
47     // invalid
48     {nullptr, 0},
49     // up to 3 operands in GPRs
50     {&PartMappings[PMI_GPR - PMI_Min], 1},
51     {&PartMappings[PMI_GPR - PMI_Min], 1},
52     {&PartMappings[PMI_GPR - PMI_Min], 1},
53     // up to 3 ops operands FPRs - single precission
54     {&PartMappings[PMI_SPR - PMI_Min], 1},
55     {&PartMappings[PMI_SPR - PMI_Min], 1},
56     {&PartMappings[PMI_SPR - PMI_Min], 1},
57     // up to 3 ops operands FPRs - double precission
58     {&PartMappings[PMI_DPR - PMI_Min], 1},
59     {&PartMappings[PMI_DPR - PMI_Min], 1},
60     {&PartMappings[PMI_DPR - PMI_Min], 1}
61 };
62 
63 } // end namespace Mips
64 } // end namespace llvm
65 
66 using namespace llvm;
67 
68 MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI)
69     : MipsGenRegisterBankInfo() {}
70 
71 const RegisterBank &MipsRegisterBankInfo::getRegBankFromRegClass(
72     const TargetRegisterClass &RC) const {
73   using namespace Mips;
74 
75   switch (RC.getID()) {
76   case Mips::GPR32RegClassID:
77   case Mips::CPU16Regs_and_GPRMM16ZeroRegClassID:
78   case Mips::GPRMM16MovePPairFirstRegClassID:
79   case Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID:
80   case Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID:
81   case Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID:
82   case Mips::SP32RegClassID:
83   case Mips::GP32RegClassID:
84     return getRegBank(Mips::GPRBRegBankID);
85   case Mips::FGRCCRegClassID:
86   case Mips::FGR32RegClassID:
87   case Mips::FGR64RegClassID:
88   case Mips::AFGR64RegClassID:
89     return getRegBank(Mips::FPRBRegBankID);
90   default:
91     llvm_unreachable("Register class not supported");
92   }
93 }
94 
95 // Instructions where all register operands are floating point.
96 static bool isFloatingPointOpcode(unsigned Opc) {
97   switch (Opc) {
98   case TargetOpcode::G_FCONSTANT:
99   case TargetOpcode::G_FADD:
100   case TargetOpcode::G_FSUB:
101   case TargetOpcode::G_FMUL:
102   case TargetOpcode::G_FDIV:
103   case TargetOpcode::G_FABS:
104   case TargetOpcode::G_FSQRT:
105   case TargetOpcode::G_FCEIL:
106   case TargetOpcode::G_FFLOOR:
107   case TargetOpcode::G_FPEXT:
108   case TargetOpcode::G_FPTRUNC:
109     return true;
110   default:
111     return false;
112   }
113 }
114 
115 // Instructions where use operands are floating point registers.
116 // Def operands are general purpose.
117 static bool isFloatingPointOpcodeUse(unsigned Opc) {
118   switch (Opc) {
119   case TargetOpcode::G_FPTOSI:
120   case TargetOpcode::G_FPTOUI:
121   case TargetOpcode::G_FCMP:
122   case Mips::MFC1:
123   case Mips::ExtractElementF64:
124   case Mips::ExtractElementF64_64:
125     return true;
126   default:
127     return isFloatingPointOpcode(Opc);
128   }
129 }
130 
131 // Instructions where def operands are floating point registers.
132 // Use operands are general purpose.
133 static bool isFloatingPointOpcodeDef(unsigned Opc) {
134   switch (Opc) {
135   case TargetOpcode::G_SITOFP:
136   case TargetOpcode::G_UITOFP:
137   case Mips::MTC1:
138   case Mips::BuildPairF64:
139   case Mips::BuildPairF64_64:
140     return true;
141   default:
142     return isFloatingPointOpcode(Opc);
143   }
144 }
145 
146 static bool isAmbiguous(unsigned Opc) {
147   switch (Opc) {
148   case TargetOpcode::G_LOAD:
149   case TargetOpcode::G_STORE:
150   case TargetOpcode::G_PHI:
151   case TargetOpcode::G_SELECT:
152     return true;
153   default:
154     return false;
155   }
156 }
157 
158 void MipsRegisterBankInfo::AmbiguousRegDefUseContainer::addDefUses(
159     Register Reg, const MachineRegisterInfo &MRI) {
160   assert(!MRI.getType(Reg).isPointer() &&
161          "Pointers are gprb, they should not be considered as ambiguous.\n");
162   for (MachineInstr &UseMI : MRI.use_instructions(Reg)) {
163     if (UseMI.getOpcode() == TargetOpcode::COPY &&
164         !TargetRegisterInfo::isPhysicalRegister(UseMI.getOperand(0).getReg()))
165       // Copies of non-physical registers are not supported
166       return;
167 
168     DefUses.push_back(&UseMI);
169   }
170 }
171 
172 void MipsRegisterBankInfo::AmbiguousRegDefUseContainer::addUseDef(
173     Register Reg, const MachineRegisterInfo &MRI) {
174   assert(!MRI.getType(Reg).isPointer() &&
175          "Pointers are gprb, they should not be considered as ambiguous.\n");
176   MachineInstr *DefMI = MRI.getVRegDef(Reg);
177   if (DefMI->getOpcode() == TargetOpcode::COPY &&
178       !TargetRegisterInfo::isPhysicalRegister(DefMI->getOperand(1).getReg()))
179     // Copies from non-physical registers are not supported.
180     return;
181 
182   UseDefs.push_back(DefMI);
183 }
184 
185 MipsRegisterBankInfo::AmbiguousRegDefUseContainer::AmbiguousRegDefUseContainer(
186     const MachineInstr *MI) {
187   assert(isAmbiguous(MI->getOpcode()) &&
188          "Not implemented for non Ambiguous opcode.\n");
189 
190   const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
191 
192   if (MI->getOpcode() == TargetOpcode::G_LOAD)
193     addDefUses(MI->getOperand(0).getReg(), MRI);
194 
195   if (MI->getOpcode() == TargetOpcode::G_STORE)
196     addUseDef(MI->getOperand(0).getReg(), MRI);
197 
198   if (MI->getOpcode() == TargetOpcode::G_SELECT) {
199     addDefUses(MI->getOperand(0).getReg(), MRI);
200 
201     addUseDef(MI->getOperand(2).getReg(), MRI);
202     addUseDef(MI->getOperand(3).getReg(), MRI);
203   }
204 }
205 
206 bool MipsRegisterBankInfo::TypeInfoForMF::visit(const MachineInstr *MI) {
207   assert(isAmbiguous(MI->getOpcode()) && "Visiting non-Ambiguous opcode.\n");
208 
209   startVisit(MI);
210   AmbiguousRegDefUseContainer DefUseContainer(MI);
211 
212   // Visit instructions where MI's DEF operands are USED.
213   if (visitAdjacentInstrs(MI, DefUseContainer.getDefUses(), true))
214     return true;
215 
216   // Visit instructions that DEFINE MI's USE operands.
217   if (visitAdjacentInstrs(MI, DefUseContainer.getUseDefs(), false))
218     return true;
219 
220   return false;
221 }
222 
223 bool MipsRegisterBankInfo::TypeInfoForMF::visitAdjacentInstrs(
224     const MachineInstr *MI, SmallVectorImpl<MachineInstr *> &AdjacentInstrs,
225     bool isDefUse) {
226   while (!AdjacentInstrs.empty()) {
227     MachineInstr *AdjMI = AdjacentInstrs.pop_back_val();
228 
229     if (isDefUse ? isFloatingPointOpcodeUse(AdjMI->getOpcode())
230                  : isFloatingPointOpcodeDef(AdjMI->getOpcode())) {
231       setTypes(MI, InstType::FloatingPoint);
232       return true;
233     }
234 
235     // Determine InstType from register bank of phys register that is
236     // 'isDefUse ? def : use' of this copy.
237     if (AdjMI->getOpcode() == TargetOpcode::COPY) {
238       setTypesAccordingToPhysicalRegister(MI, AdjMI, isDefUse ? 0 : 1);
239       return true;
240     }
241 
242     if (isAmbiguous(AdjMI->getOpcode())) {
243       // Chains of ambiguous instructions are not supported.
244       return false;
245     }
246 
247     // Defaults to integer instruction. Includes G_MERGE_VALUES and
248     // G_UNMERGE_VALUES.
249     setTypes(MI, InstType::Integer);
250     return true;
251   }
252   return false;
253 }
254 
255 void MipsRegisterBankInfo::TypeInfoForMF::setTypes(const MachineInstr *MI,
256                                                    InstType InstTy) {
257   changeRecordedTypeForInstr(MI, InstTy);
258 }
259 
260 void MipsRegisterBankInfo::TypeInfoForMF::setTypesAccordingToPhysicalRegister(
261     const MachineInstr *MI, const MachineInstr *CopyInst, unsigned Op) {
262   assert((TargetRegisterInfo::isPhysicalRegister(
263              CopyInst->getOperand(Op).getReg())) &&
264          "Copies of non physical registers should not be considered here.\n");
265 
266   const MachineFunction &MF = *CopyInst->getMF();
267   const MachineRegisterInfo &MRI = MF.getRegInfo();
268   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
269   const RegisterBankInfo &RBI =
270       *CopyInst->getMF()->getSubtarget().getRegBankInfo();
271   const RegisterBank *Bank =
272       RBI.getRegBank(CopyInst->getOperand(Op).getReg(), MRI, TRI);
273 
274   if (Bank == &Mips::FPRBRegBank)
275     setTypes(MI, InstType::FloatingPoint);
276   else if (Bank == &Mips::GPRBRegBank)
277     setTypes(MI, InstType::Integer);
278   else
279     llvm_unreachable("Unsupported register bank.\n");
280 }
281 
282 MipsRegisterBankInfo::InstType
283 MipsRegisterBankInfo::TypeInfoForMF::determineInstType(const MachineInstr *MI) {
284   visit(MI);
285   return getRecordedTypeForInstr(MI);
286 }
287 
288 void MipsRegisterBankInfo::TypeInfoForMF::cleanupIfNewFunction(
289     llvm::StringRef FunctionName) {
290   if (MFName != FunctionName) {
291     MFName = FunctionName;
292     Types.clear();
293   }
294 }
295 
296 const RegisterBankInfo::InstructionMapping &
297 MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
298 
299   static TypeInfoForMF TI;
300 
301   // Reset TI internal data when MF changes.
302   TI.cleanupIfNewFunction(MI.getMF()->getName());
303 
304   unsigned Opc = MI.getOpcode();
305   const MachineFunction &MF = *MI.getParent()->getParent();
306   const MachineRegisterInfo &MRI = MF.getRegInfo();
307 
308   const RegisterBankInfo::InstructionMapping &Mapping = getInstrMappingImpl(MI);
309   if (Mapping.isValid())
310     return Mapping;
311 
312   using namespace TargetOpcode;
313 
314   unsigned NumOperands = MI.getNumOperands();
315   const ValueMapping *OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
316   unsigned MappingID = DefaultMappingID;
317   const unsigned CustomMappingID = 1;
318 
319   switch (Opc) {
320   case G_TRUNC:
321   case G_ADD:
322   case G_SUB:
323   case G_MUL:
324   case G_UMULH:
325   case G_ZEXTLOAD:
326   case G_SEXTLOAD:
327   case G_GEP:
328   case G_AND:
329   case G_OR:
330   case G_XOR:
331   case G_SHL:
332   case G_ASHR:
333   case G_LSHR:
334   case G_SDIV:
335   case G_UDIV:
336   case G_SREM:
337   case G_UREM:
338     OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
339     break;
340   case G_LOAD: {
341     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
342     InstType InstTy = InstType::Integer;
343     if (!MRI.getType(MI.getOperand(0).getReg()).isPointer()) {
344       InstTy = TI.determineInstType(&MI);
345     }
346 
347     if (InstTy == InstType::FloatingPoint) { // fprb
348       OperandsMapping =
349           getOperandsMapping({Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
350                                          : &Mips::ValueMappings[Mips::DPRIdx],
351                               &Mips::ValueMappings[Mips::GPRIdx]});
352       break;
353     } else { // gprb
354       OperandsMapping =
355           getOperandsMapping({Size <= 32 ? &Mips::ValueMappings[Mips::GPRIdx]
356                                          : &Mips::ValueMappings[Mips::DPRIdx],
357                               &Mips::ValueMappings[Mips::GPRIdx]});
358       if (Size == 64)
359         MappingID = CustomMappingID;
360     }
361 
362     break;
363   }
364   case G_STORE: {
365     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
366     InstType InstTy = InstType::Integer;
367     if (!MRI.getType(MI.getOperand(0).getReg()).isPointer()) {
368       InstTy = TI.determineInstType(&MI);
369     }
370 
371     if (InstTy == InstType::FloatingPoint) { // fprb
372       OperandsMapping =
373           getOperandsMapping({Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
374                                          : &Mips::ValueMappings[Mips::DPRIdx],
375                               &Mips::ValueMappings[Mips::GPRIdx]});
376       break;
377     } else { // gprb
378       OperandsMapping =
379           getOperandsMapping({Size <= 32 ? &Mips::ValueMappings[Mips::GPRIdx]
380                                          : &Mips::ValueMappings[Mips::DPRIdx],
381                               &Mips::ValueMappings[Mips::GPRIdx]});
382       if (Size == 64)
383         MappingID = CustomMappingID;
384     }
385     break;
386   }
387   case G_SELECT: {
388     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
389     InstType InstTy = InstType::Integer;
390     if (!MRI.getType(MI.getOperand(0).getReg()).isPointer()) {
391       InstTy = TI.determineInstType(&MI);
392     }
393 
394     if (InstTy == InstType::FloatingPoint) { // fprb
395       const RegisterBankInfo::ValueMapping *Bank =
396           Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
397                      : &Mips::ValueMappings[Mips::DPRIdx];
398       OperandsMapping = getOperandsMapping(
399           {Bank, &Mips::ValueMappings[Mips::GPRIdx], Bank, Bank});
400       break;
401     } else { // gprb
402       const RegisterBankInfo::ValueMapping *Bank =
403           Size <= 32 ? &Mips::ValueMappings[Mips::GPRIdx]
404                      : &Mips::ValueMappings[Mips::DPRIdx];
405       OperandsMapping = getOperandsMapping(
406           {Bank, &Mips::ValueMappings[Mips::GPRIdx], Bank, Bank});
407       if (Size == 64)
408         MappingID = CustomMappingID;
409     }
410     break;
411   }
412   case G_UNMERGE_VALUES: {
413     OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx],
414                                           &Mips::ValueMappings[Mips::GPRIdx],
415                                           &Mips::ValueMappings[Mips::DPRIdx]});
416     MappingID = CustomMappingID;
417     break;
418   }
419   case G_MERGE_VALUES: {
420     OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::DPRIdx],
421                                           &Mips::ValueMappings[Mips::GPRIdx],
422                                           &Mips::ValueMappings[Mips::GPRIdx]});
423     MappingID = CustomMappingID;
424     break;
425   }
426   case G_FADD:
427   case G_FSUB:
428   case G_FMUL:
429   case G_FDIV:
430   case G_FABS:
431   case G_FSQRT:{
432     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
433     assert((Size == 32 || Size == 64) && "Unsupported floating point size");
434     OperandsMapping = Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
435                                  : &Mips::ValueMappings[Mips::DPRIdx];
436     break;
437   }
438   case G_FCONSTANT: {
439     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
440     assert((Size == 32 || Size == 64) && "Unsupported floating point size");
441     const RegisterBankInfo::ValueMapping *FPRValueMapping =
442         Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
443                    : &Mips::ValueMappings[Mips::DPRIdx];
444     OperandsMapping = getOperandsMapping({FPRValueMapping, nullptr});
445     break;
446   }
447   case G_FCMP: {
448     unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
449     assert((Size == 32 || Size == 64) && "Unsupported floating point size");
450     const RegisterBankInfo::ValueMapping *FPRValueMapping =
451         Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
452                    : &Mips::ValueMappings[Mips::DPRIdx];
453     OperandsMapping =
454         getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr,
455                             FPRValueMapping, FPRValueMapping});
456     break;
457   }
458   case G_FPEXT:
459     OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::DPRIdx],
460                                           &Mips::ValueMappings[Mips::SPRIdx]});
461     break;
462   case G_FPTRUNC:
463     OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::SPRIdx],
464                                           &Mips::ValueMappings[Mips::DPRIdx]});
465     break;
466   case G_FPTOSI: {
467     unsigned SizeFP = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
468     assert((MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() == 32) &&
469            "Unsupported integer size");
470     assert((SizeFP == 32 || SizeFP == 64) && "Unsupported floating point size");
471     OperandsMapping = getOperandsMapping({
472         &Mips::ValueMappings[Mips::GPRIdx],
473         SizeFP == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
474                      : &Mips::ValueMappings[Mips::DPRIdx],
475     });
476     break;
477   }
478   case G_SITOFP: {
479     unsigned SizeInt = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
480     unsigned SizeFP = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
481     (void)SizeInt;
482     assert((SizeInt == 32) && "Unsupported integer size");
483     assert((SizeFP == 32 || SizeFP == 64) && "Unsupported floating point size");
484     OperandsMapping =
485         getOperandsMapping({SizeFP == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
486                                          : &Mips::ValueMappings[Mips::DPRIdx],
487                             &Mips::ValueMappings[Mips::GPRIdx]});
488     break;
489   }
490   case G_CONSTANT:
491   case G_FRAME_INDEX:
492   case G_GLOBAL_VALUE:
493   case G_BRCOND:
494     OperandsMapping =
495         getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr});
496     break;
497   case G_ICMP:
498     OperandsMapping =
499         getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr,
500                             &Mips::ValueMappings[Mips::GPRIdx],
501                             &Mips::ValueMappings[Mips::GPRIdx]});
502     break;
503   default:
504     return getInvalidInstructionMapping();
505   }
506 
507   return getInstructionMapping(MappingID, /*Cost=*/1, OperandsMapping,
508                                NumOperands);
509 }
510 
511 using InstListTy = GISelWorkList<4>;
512 namespace {
513 class InstManager : public GISelChangeObserver {
514   InstListTy &InstList;
515 
516 public:
517   InstManager(InstListTy &Insts) : InstList(Insts) {}
518 
519   void createdInstr(MachineInstr &MI) override { InstList.insert(&MI); }
520   void erasingInstr(MachineInstr &MI) override {}
521   void changingInstr(MachineInstr &MI) override {}
522   void changedInstr(MachineInstr &MI) override {}
523 };
524 } // end anonymous namespace
525 
526 /// Here we have to narrowScalar s64 operands to s32, combine away
527 /// G_MERGE/G_UNMERGE and erase instructions that became dead in the process.
528 /// We manually assign 32 bit gprb to register operands of all new instructions
529 /// that got created in the process since they will not end up in RegBankSelect
530 /// loop. Careful not to delete instruction after MI i.e. MI.getIterator()++.
531 void MipsRegisterBankInfo::applyMappingImpl(
532     const OperandsMapper &OpdMapper) const {
533   MachineInstr &MI = OpdMapper.getMI();
534   InstListTy NewInstrs;
535   MachineIRBuilder B(MI);
536   MachineFunction *MF = MI.getMF();
537   MachineRegisterInfo &MRI = OpdMapper.getMRI();
538 
539   InstManager NewInstrObserver(NewInstrs);
540   GISelObserverWrapper WrapperObserver(&NewInstrObserver);
541   LegalizerHelper Helper(*MF, WrapperObserver, B);
542   LegalizationArtifactCombiner ArtCombiner(
543       B, MF->getRegInfo(), *MF->getSubtarget().getLegalizerInfo());
544 
545   switch (MI.getOpcode()) {
546   case TargetOpcode::G_LOAD:
547   case TargetOpcode::G_STORE:
548   case TargetOpcode::G_SELECT: {
549     Helper.narrowScalar(MI, 0, LLT::scalar(32));
550     // Handle new instructions.
551     while (!NewInstrs.empty()) {
552       MachineInstr *NewMI = NewInstrs.pop_back_val();
553       // This is new G_UNMERGE that was created during narrowScalar and will
554       // not be considered for regbank selection. RegBankSelect for mips
555       // visits/makes corresponding G_MERGE first. Combine them here.
556       if (NewMI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES) {
557         SmallVector<MachineInstr *, 2> DeadInstrs;
558         ArtCombiner.tryCombineMerges(*NewMI, DeadInstrs);
559         for (MachineInstr *DeadMI : DeadInstrs)
560           DeadMI->eraseFromParent();
561       }
562       // This G_MERGE will be combined away when its corresponding G_UNMERGE
563       // gets regBankSelected.
564       else if (NewMI->getOpcode() == TargetOpcode::G_MERGE_VALUES)
565         continue;
566       else
567         // Manually set register banks for all register operands to 32 bit gprb.
568         for (auto Op : NewMI->operands()) {
569           if (Op.isReg()) {
570             assert(MRI.getType(Op.getReg()).getSizeInBits() == 32 &&
571                    "Only 32 bit gprb is handled here.\n");
572             MRI.setRegBank(Op.getReg(), getRegBank(Mips::GPRBRegBankID));
573           }
574         }
575     }
576     return;
577   }
578   case TargetOpcode::G_UNMERGE_VALUES: {
579     SmallVector<MachineInstr *, 2> DeadInstrs;
580     ArtCombiner.tryCombineMerges(MI, DeadInstrs);
581     for (MachineInstr *DeadMI : DeadInstrs)
582       DeadMI->eraseFromParent();
583     return;
584   }
585   default:
586     break;
587   }
588 
589   return applyDefaultMapping(OpdMapper);
590 }
591