[ARM] GlobalISel: Legalize s8 and s16 G_(S|U)DIV

We have to widen the operands to 32 bits and then we can either use
hardware division if it is available or lower to a libcall otherwise.

At the mom

[ARM] GlobalISel: Legalize s8 and s16 G_(S|U)DIV

We have to widen the operands to 32 bits and then we can either use
hardware division if it is available or lower to a libcall otherwise.

At the moment it is not enough to set the Legalizer action to
WidenScalar, since for libcalls it won't know what to do (it won't be
able to find what size to widen to, because it will find Libcall and not
Legal for 32 bits). To hack around this limitation, we request Custom
lowering, and as part of that we widen first and then we run another
legalizeInstrStep on the widened DIV.

llvm-svn: 301166

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[ARM] GlobalISel: Support G_(S|U)DIV for s32

Add support for both targets with hardware division and without. For
hardware division we have to add support throughout the pipeline
(legalizer, reg ban

[ARM] GlobalISel: Support G_(S|U)DIV for s32

Add support for both targets with hardware division and without. For
hardware division we have to add support throughout the pipeline
(legalizer, reg bank select, instruction select). For targets without
hardware division, we only need to mark it as a libcall.

llvm-svn: 301164

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[ARM] GlobalISel: Add support for G_MUL

Support G_MUL, very similar to G_ADD and G_SUB. The only difference is
in the instruction selector, where we have to select either MUL or MULv5
depending on t

[ARM] GlobalISel: Add support for G_MUL

Support G_MUL, very similar to G_ADD and G_SUB. The only difference is
in the instruction selector, where we have to select either MUL or MULv5
depending on the target.

llvm-svn: 300665

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[ARM] GlobalISel: Add support for G_SUB

Support G_SUB throughout the GlobalISel pipeline. It is exactly the same
as G_ADD, nothing fancy.

llvm-svn: 300546

GlobalISel: Allow legalizing G_FADD to a libcall

Use the same handling in the generic legalizer code as for the other
libcalls (G_FREM, G_FPOW).

Enable it on ARM for float and double so we can test

GlobalISel: Allow legalizing G_FADD to a libcall

Use the same handling in the generic legalizer code as for the other
libcalls (G_FREM, G_FPOW).

Enable it on ARM for float and double so we can test it.

llvm-svn: 299931

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[ARM] GlobalISel: Support G_FPOW for float and double

Legalize to a libcall.

llvm-svn: 299841

[ARM] GlobalISel: Support frem for 64-bit values

Legalize to a libcall.

llvm-svn: 299756

[ARM] GlobalISel: Support frem for 32-bit values

Legalize to a libcall.
On this occasion, also start allowing soft float subtargets. For the
moment G_FREM is the only legal floating point operation

[ARM] GlobalISel: Support frem for 32-bit values

Legalize to a libcall.
On this occasion, also start allowing soft float subtargets. For the
moment G_FREM is the only legal floating point operation for them.

llvm-svn: 299753

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[ARM] GlobalISel: Legalize 32-bit constants

llvm-svn: 296468

[ARM] GlobalISel: Legalize G_GEP with 32-bit offsets

At the moment we're only interested in GEPs for putting call parameters on the
stack, so we'll stick to 32-bit offsets.

llvm-svn: 296452

[ARM] GlobalISel: Legalize stores

Allow the same types that we allow for loads.

llvm-svn: 296108

Revert "[ARM] GlobalISel: Legalize stores"

This reverts commit r296103 because the test broke on one of the bots. Sorry!

llvm-svn: 296104

[ARM] GlobalISel: Legalize stores

Allow the same types that we allow for loads.

llvm-svn: 296103

[ARM] GlobalISel: Use Subtarget in Legalizer

Start using the Subtarget to make decisions about what's legal. In particular,
we only mark floating point operations as legal if we have VFP2, which is

[ARM] GlobalISel: Use Subtarget in Legalizer

Start using the Subtarget to make decisions about what's legal. In particular,
we only mark floating point operations as legal if we have VFP2, which is
something we should've done from the very start.

llvm-svn: 295439

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[ARM] GlobalISel: Legalize 64-bit G_FADD and G_LOAD

For now we just mark them as legal all the time and let the other passes bail
out if they can't handle it. In the future, we'll want to move more

[ARM] GlobalISel: Legalize 64-bit G_FADD and G_LOAD

For now we just mark them as legal all the time and let the other passes bail
out if they can't handle it. In the future, we'll want to move more of the
brains into the legalizer.

llvm-svn: 295300

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[ARM] GlobalISel: Add FPR reg bank

Add a register bank for floating point values and select simple instructions
using them (add, copies from GPR).

This assumes that the hardware can cope with a sin

[ARM] GlobalISel: Add FPR reg bank

Add a register bank for floating point values and select simple instructions
using them (add, copies from GPR).

This assumes that the hardware can cope with a single precision add (VADDS)
instruction, so the legalizer will treat G_FADD as legal and the instruction
selector will refuse to select if the hardware doesn't support it. In the future
we'll want to be more careful about this, and legalize to libcalls if we have to
use soft float.

llvm-svn: 294442

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[ARM] GlobalISel: Legalize loading pointers

Make it legal to load pointer values. Also check that pointers are assigned
to the GPR reg bank by default.

llvm-svn: 293886

[ARM][LegalizerInfo] Specify the type of the opcode.

This is to fix the win7 bot that does not seem to be very
good at infering the type when it gets used in an initiliazer list.

llvm-svn: 293248

[ARM] GlobalISel: Load i1, i8 and i16 args from stack

Add support for loading i1, i8 and i16 arguments from the stack, with or without
the ABI extension flags.

When the ABI extension flags are pres

[ARM] GlobalISel: Load i1, i8 and i16 args from stack

Add support for loading i1, i8 and i16 arguments from the stack, with or without
the ABI extension flags.

When the ABI extension flags are present, we load a 4-byte value, otherwise we
preserve the size of the load and let the instruction selector replace it with a
LDRB/LDRH. This generates the same thing as DAGISel.

Differential Revision: https://reviews.llvm.org/D27803

llvm-svn: 293163

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[ARM] GlobalISel: Support i1 add and ABI extensions

Add support for:
* i1 add
* i1 function arguments, if passed through registers
* i1 returns, with ABI signext/zeroext

Differential Revision: http

[ARM] GlobalISel: Support i1 add and ABI extensions

Add support for:
* i1 add
* i1 function arguments, if passed through registers
* i1 returns, with ABI signext/zeroext

Differential Revision: https://reviews.llvm.org/D27706

llvm-svn: 293035

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[ARM] GlobalISel: Support i8/i16 ABI extensions

At the moment, this means supporting the signext/zeroext attribute on the return
type of the function. For function arguments, signext/zeroext should

[ARM] GlobalISel: Support i8/i16 ABI extensions

At the moment, this means supporting the signext/zeroext attribute on the return
type of the function. For function arguments, signext/zeroext should be handled
by the caller, so there's nothing for us to do until we start lowering calls.

Note that this does not include support for other extensions (i8 to i16), those
will be added later.

Differential Revision: https://reviews.llvm.org/D27705

llvm-svn: 293034

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[ARM] GlobalISel: Allow i8 and i16 adds

Teach the instruction selector and legalizer that it's ok to have adds with 8 or
16-bit integers.

This is the second part of https://reviews.llvm.org/D27704

[ARM] GlobalISel: Allow i8 and i16 adds

Teach the instruction selector and legalizer that it's ok to have adds with 8 or
16-bit integers.

This is the second part of https://reviews.llvm.org/D27704

llvm-svn: 290105

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[ARM] GlobalISel: Support loading from the stack

Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit
scalars only). This will be useful for functions that need to pass arg

[ARM] GlobalISel: Support loading from the stack

Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit
scalars only). This will be useful for functions that need to pass arguments on
the stack.

First part of https://reviews.llvm.org/D27195.

llvm-svn: 290096

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[ARM] GlobalISel: Select add i32, i32

Add the minimal support necessary to select a function that returns the sum of
two i32 values.

This includes some support for argument/return lowering of i32 v

[ARM] GlobalISel: Select add i32, i32

Add the minimal support necessary to select a function that returns the sum of
two i32 values.

This includes some support for argument/return lowering of i32 values through
registers, as well as the handling of copy and add instructions throughout the
GlobalISel pipeline.

Differential Revision: https://reviews.llvm.org/D26677

llvm-svn: 289940

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[ARM] Add plumbing for GlobalISel

Add GlobalISel skeleton, up to the point where we can select a ret void.

llvm-svn: 286573