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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6 |
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85142f5b |
| 09-Dec-2024 |
Brox Chen <guochen2@amd.com> |
[AMDGPU][True16][CodeGen] support for true16 for vinterp 16bit instructions (#116702)
vinterp 16bit instructions codeGen support in True16 format
Currently only enable two tests, will enable more
[AMDGPU][True16][CodeGen] support for true16 for vinterp 16bit instructions (#116702)
vinterp 16bit instructions codeGen support in True16 format
Currently only enable two tests, will enable more when more true16
instructions are supported
show more ...
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3f3bcac5 |
| 06-Dec-2024 |
Jay Foad <jay.foad@amd.com> |
[AMDGPU] New alias v_interp_p2_new_f32 (#118968)
This is for compatibility with SP3. Also add basic testing for the new
GFX11 VINTERP encoding.
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Revision tags: llvmorg-19.1.5, llvmorg-19.1.4 |
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58f107f3 |
| 15-Nov-2024 |
Jay Foad <jay.foad@amd.com> |
[AMDGPU] Remove unused template argument after #113634. NFC.
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abff8fe2 |
| 14-Nov-2024 |
Brox Chen <guochen2@amd.com> |
[AMDGPU][True16][MC] VINTERP instructions supporting true16/fake16 (#113634)
Update VInterp instructions with true16 and fake16 formats.
This patch includes instructions:
v_interp_p10_f16_f32
v
[AMDGPU][True16][MC] VINTERP instructions supporting true16/fake16 (#113634)
Update VInterp instructions with true16 and fake16 formats.
This patch includes instructions:
v_interp_p10_f16_f32
v_interp_p2_f16_f32
v_interp_p10_rtz_f16_f32
v_interp_p2_rtz_f16_f32
dasm test vinterp-fake16.txt is removed and the testline are merged into
vinterp.txt which handles both true16/fake16 cases
show more ...
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Revision tags: llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7 |
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| #
6b91a3be |
| 04-Jun-2024 |
Ivan Kosarev <ivan.kosarev@amd.com> |
[AMDGPU][NFC] Rename the clamp modifier definition to follow the prevailing convention. (#94353)
Allows to simplify the definition itself.
Part of <https://github.com/llvm/llvm-project/issues/626
[AMDGPU][NFC] Rename the clamp modifier definition to follow the prevailing convention. (#94353)
Allows to simplify the definition itself.
Part of <https://github.com/llvm/llvm-project/issues/62629>.
show more ...
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Revision tags: llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3 |
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216b5e96 |
| 01-Apr-2024 |
Ruiling, Song <ruiling.song@amd.com> |
[AMDGPU] Expose RTZ version of f16 interpolation for gfx11+ (#86614)
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Revision tags: llvmorg-18.1.2 |
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addda68f |
| 08-Mar-2024 |
Changpeng Fang <changpeng.fang@amd.com> |
AMDGPU: Rename HasVinterInsts to HasVINTERPEncoding, NFC (#84535)
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Revision tags: llvmorg-18.1.1 |
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49ec8b74 |
| 06-Mar-2024 |
Changpeng Fang <changpeng.fang@amd.com> |
AMDGPU: Define and Use HasInterpInsts for interp inst definitions (#84102)
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Revision tags: llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1 |
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4b8e55cb |
| 25-Jan-2024 |
Ivan Kosarev <ivan.kosarev@amd.com> |
[AMDGPU][AsmParser][NFC] Rename integer modifier operands to follow the convention. (#79284)
Part of <https://github.com/llvm/llvm-project/issues/62629>.
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Revision tags: llvmorg-19-init |
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19f4cec6 |
| 07-Dec-2023 |
Jay Foad <jay.foad@amd.com> |
[AMDGPU] Add GFX12 encoding for VINTERP instructions (#74616)
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Revision tags: llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3 |
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b1883aae |
| 09-Feb-2023 |
Jay Foad <jay.foad@amd.com> |
[AMDGPU] Ignore unused bits in VINTERP encoding
In the GFX11 VINTERP encoding bits 23, 59 and 60 are unused. Change the
disassembler to ignore these bits.
Differential Revision: https://reviews.llv
[AMDGPU] Ignore unused bits in VINTERP encoding
In the GFX11 VINTERP encoding bits 23, 59 and 60 are unused. Change the
disassembler to ignore these bits.
Differential Revision: https://reviews.llvm.org/D143633
show more ...
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Revision tags: llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5 |
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8f689521 |
| 07-Nov-2022 |
Dmitry Preobrazhensky <dmitri.preobrazhenski@gmail.com> |
[AMDGPU][MC][GFX11][NFC] Correct VINTERP src operands
Differential Revision: https://reviews.llvm.org/D137238
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Revision tags: llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5 |
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| #
20d20156 |
| 09-Jun-2022 |
Joe Nash <Joseph.Nash@amd.com> |
[AMDGPU] gfx11 VINTERP intrinsics and ISel support
Depends on D127664
Reviewed By: rampitec, #amdgpu
Differential Revision: https://reviews.llvm.org/D127756
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Revision tags: llvmorg-14.0.4, llvmorg-14.0.3 |
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| #
ef1ea5ac |
| 27-Apr-2022 |
Joe Nash <Joseph.Nash@amd.com> |
[AMDGPU] gfx11 vinterp instructions MC support
A new instruction encoding. Some of these instructions were previously VOP3
encoded.
Contributors:
Carl Ritson <carl.ritson@amd.com>
Patch 11/N for u
[AMDGPU] gfx11 vinterp instructions MC support
A new instruction encoding. Some of these instructions were previously VOP3
encoded.
Contributors:
Carl Ritson <carl.ritson@amd.com>
Patch 11/N for upstreaming of AMDGPU gfx11 architecture.
Depends on D125824
Reviewed By: critson
Differential Revision: https://reviews.llvm.org/D125989
show more ...
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