History log of /llvm-project/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp (Results 76 – 100 of 229)
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# 323ef0eb 09-Apr-2021 Jay Foad <jay.foad@amd.com>

[AMDGPU] SIFoldOperands: eagerly erase dead REG_SEQUENCEs

This is fairly cheap to implement and means less work for future
passes like MachineDCE.

Reapply with a fix for using InstToErase after it

[AMDGPU] SIFoldOperands: eagerly erase dead REG_SEQUENCEs

This is fairly cheap to implement and means less work for future
passes like MachineDCE.

Reapply with a fix for using InstToErase after it had been erased.

Differential Revision: https://reviews.llvm.org/D100188

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# 3d4730a7 09-Apr-2021 Mitch Phillips <31459023+hctim@users.noreply.github.com>

Revert "[AMDGPU] SIFoldOperands: eagerly erase dead REG_SEQUENCEs"

This reverts commit d19a42eba98fe853dd52f7dc89d8cd2727c7fc1c.

Reason: Broke the ASan buildbots. See the original phabricator revie

Revert "[AMDGPU] SIFoldOperands: eagerly erase dead REG_SEQUENCEs"

This reverts commit d19a42eba98fe853dd52f7dc89d8cd2727c7fc1c.

Reason: Broke the ASan buildbots. See the original phabricator review
for more details: https://reviews.llvm.org/D100188

show more ...


# d19a42eb 09-Apr-2021 Jay Foad <jay.foad@amd.com>

[AMDGPU] SIFoldOperands: eagerly erase dead REG_SEQUENCEs

This is fairly cheap to implement and means less work for future
passes like MachineDCE.

Differential Revision: https://reviews.llvm.org/D1

[AMDGPU] SIFoldOperands: eagerly erase dead REG_SEQUENCEs

This is fairly cheap to implement and means less work for future
passes like MachineDCE.

Differential Revision: https://reviews.llvm.org/D100188

show more ...


# a4ced03d 08-Apr-2021 Jay Foad <jay.foad@amd.com>

[AMDGPU] SIFoldOperands: eagerly delete dead copies

This is cheap to implement, means less work for future passes like
MachineDCE, and slightly improves the folding in some cases.

Differential Revi

[AMDGPU] SIFoldOperands: eagerly delete dead copies

This is cheap to implement, means less work for future passes like
MachineDCE, and slightly improves the folding in some cases.

Differential Revision: https://reviews.llvm.org/D100117

show more ...


# a1a372df 08-Apr-2021 Jay Foad <jay.foad@amd.com>

[AMDGPU] SIFoldOperands: remove an unneeded isReg check. NFC.


# a250e91d 08-Apr-2021 Jay Foad <jay.foad@amd.com>

[AMDGPU] SIFoldOperands: make use of emplace_back. NFC.


# 2724b57e 08-Apr-2021 Jay Foad <jay.foad@amd.com>

[AMDGPU] SIFoldOperands: remove an unneeded make_early_inc_range. NFC.


# c28f79a0 08-Apr-2021 Jay Foad <jay.foad@amd.com>

[AMDGPU] SIFoldOperands: try harder to fold cndmask instructions

Look through copies to find more cases where the two values being
selected are identical. The motivation for this is just to be able

[AMDGPU] SIFoldOperands: try harder to fold cndmask instructions

Look through copies to find more cases where the two values being
selected are identical. The motivation for this is just to be able to
remove the weird special case where tryFoldCndMask was called from
foldInstOperand, part way through folding a move-immediate into its
users, without regressing any lit tests.

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# 3344cd3a 08-Apr-2021 Jay Foad <jay.foad@amd.com>

[AMDGPU] SIFoldOperands: make tryFoldCndMask a member function. NFC.


# 94a6fe43 08-Apr-2021 Jay Foad <jay.foad@amd.com>

[AMDGPU] SIFoldOperands: refactor tryFoldCndMask with early-outs. NFC.


# bf6cab6f 07-Apr-2021 Jay Foad <jay.foad@amd.com>

[AMDGPU] SIFoldOperands: don't dump extra '\n' after MachineInstr. NFC.


# 8f798566 06-Apr-2021 Jay Foad <jay.foad@amd.com>

[AMDGPU] SIFoldOperands: use isUseMIInFoldList. NFC.


Revision tags: llvmorg-12.0.0, llvmorg-12.0.0-rc5
# efc7bf27 06-Apr-2021 Jay Foad <jay.foad@amd.com>

[AMDGPU] SIFoldOperands: use MachineRegisterInfo::hasOneNonDBGUser

NFC.


# 005dcd19 06-Apr-2021 Jay Foad <jay.foad@amd.com>

[AMDGPU] SIFoldOperands: use range-based loops and make_early_inc_range

NFC.


Revision tags: llvmorg-12.0.0-rc4
# ce9cca6c 31-Mar-2021 Jay Foad <jay.foad@amd.com>

[AMDGPU] SIFoldOperands: rename tryFoldInst to tryFoldCndMask

This follows the pattern of the other tryFold* functions. NFC.


# cf4f5292 31-Mar-2021 Jay Foad <jay.foad@amd.com>

[AMDGPU] SIFoldOperands: use getVRegDef instead of getUniqueVRegDef

We are in SSA so getVRegDef is equivalent but simpler. NFC.


# 65c8bfb5 25-Mar-2021 Brendon Cahoon <brendon.cahoon@amd.com>

[AMDGPU] Enable output modifiers for double precision instructions

Update SIFoldOperands pass to recognize v_add_f64 and v_mul_f64
instructions for folding output modifiers.

Differential Revision:

[AMDGPU] Enable output modifiers for double precision instructions

Update SIFoldOperands pass to recognize v_add_f64 and v_mul_f64
instructions for folding output modifiers.

Differential Revision: https://reviews.llvm.org/D99505

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# 619b8884 29-Mar-2021 Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>

[AMDGPU] Fix "Sequence" spelling. NFC.


Revision tags: llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2
# a8d9d507 17-Feb-2021 Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>

[AMDGPU] gfx90a support

Differential Revision: https://reviews.llvm.org/D96906


Revision tags: llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2
# ff8a1cae 15-Jan-2021 Christudasan Devadasan <Christudasan.Devadasan@amd.com>

[AMDGPU] Fix the inconsistency in soffset for MUBUF stack accesses.

During instruction selection, there is an inconsistency in choosing
the initial soffset value. With certain early passes, this val

[AMDGPU] Fix the inconsistency in soffset for MUBUF stack accesses.

During instruction selection, there is an inconsistency in choosing
the initial soffset value. With certain early passes, this value is
getting modified and that brought additional fixup during
eliminateFrameIndex to work for all cases. This whole transformation
looks trivial and can be handled better.

This patch clearly defines the initial value for soffset and keeps it
unchanged before eliminateFrameIndex. The initial value must be zero
for MUBUF with a frame index. The non-frame index MUBUF forms that
use a raw offset from SP will have the stack register for soffset.
During frame elimination, the soffset remains zero for entry functions
with zero dynamic allocas and no callsites, or else is updated to the
appropriate frame/stack register.

Also, did some code clean up and made all asserts around soffset
stricter to match.

Reviewed By: scott.linder

Differential Revision: https://reviews.llvm.org/D95071

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# 560d7e04 20-Jan-2021 dfukalov <daniil.fukalov@amd.com>

[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets

... to reduce headers dependency.

Reviewed By: rampitec, arsenm

Differential Revision: https://reviews.llvm.org/D95036


Revision tags: llvmorg-11.1.0-rc1
# 314e29ed 07-Jan-2021 Joe Nash <Joseph.Nash@amd.com>

[AMDGPU] Add _e64 suffix to VOP3 Insts

Previously, instructions which could be
expressed as VOP3 in addition to another
encoding had a _e64 suffix on the tablegen
record name, while those
only avail

[AMDGPU] Add _e64 suffix to VOP3 Insts

Previously, instructions which could be
expressed as VOP3 in addition to another
encoding had a _e64 suffix on the tablegen
record name, while those
only available as VOP3 did not. With this
patch, all VOP3s will have the _e64 suffix.
The assembly does not change, only the mir.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D94341

Change-Id: Ia8ec8890d47f8f94bbbdac43745b4e9dd2b03423

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# 6a87e9b0 25-Dec-2020 dfukalov <daniil.fukalov@amd.com>

[NFC][AMDGPU] Reduce include files dependency.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D93813


# 3914bebe 04-Jan-2021 Jay Foad <jay.foad@amd.com>

[AMDGPU] Handle v_fmac_legacy_f32 in SIFoldOperands

Convert it to v_fma_legacy_f32 if it is profitable to do so, just like
other mac instructions that are converted to their mad equivalents.

Differ

[AMDGPU] Handle v_fmac_legacy_f32 in SIFoldOperands

Convert it to v_fma_legacy_f32 if it is profitable to do so, just like
other mac instructions that are converted to their mad equivalents.

Differential Revision: https://reviews.llvm.org/D94010

show more ...


# 4e6054a8 04-Jan-2021 Jay Foad <jay.foad@amd.com>

[AMDGPU] Split out new helper function macToMad in SIFoldOperands. NFC.

Differential Revision: https://reviews.llvm.org/D94009


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