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Revision tags: llvmorg-21-init, llvmorg-19.1.7 |
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f15da5fb |
| 13-Jan-2025 |
Shilei Tian <i@tianshilei.me> |
[AMDGPU] Fix an invalid cast in `AMDGPULateCodeGenPrepare::visitLoadInst` (#122494)
Fixes: SWDEV-507695
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Revision tags: llvmorg-19.1.6 |
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f9f7c42c |
| 05-Dec-2024 |
Jay Foad <jay.foad@amd.com> |
[AMDGPU] Refine AMDGPULateCodeGenPrepare class. NFC. (#118792)
Use references instead of pointers for most state and initialize it all
in the constructor, and similarly for the LiveRegOptimizer cla
[AMDGPU] Refine AMDGPULateCodeGenPrepare class. NFC. (#118792)
Use references instead of pointers for most state and initialize it all
in the constructor, and similarly for the LiveRegOptimizer class.
show more ...
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Revision tags: llvmorg-19.1.5 |
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3923e045 |
| 28-Nov-2024 |
Jay Foad <jay.foad@amd.com> |
[AMDGPU] Preserve all analyses if nothing changed (#117994)
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Revision tags: llvmorg-19.1.4 |
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be187369 |
| 14-Nov-2024 |
Kazu Hirata <kazu@google.com> |
[AMDGPU] Remove unused includes (NFC) (#116154)
Identified with misc-include-cleaner.
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Revision tags: llvmorg-19.1.3 |
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0cb80c4f |
| 23-Oct-2024 |
Kazu Hirata <kazu@google.com> |
[AMDGPU] Avoid repeated hash lookups (NFC) (#113409)
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Revision tags: llvmorg-19.1.2 |
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8d13e7b8 |
| 03-Oct-2024 |
Jay Foad <jay.foad@amd.com> |
[AMDGPU] Qualify auto. NFC. (#110878)
Generated automatically with:
$ clang-tidy -fix -checks=-*,llvm-qualified-auto $(find
lib/Target/AMDGPU/ -type f)
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Revision tags: llvmorg-19.1.1 |
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d7db0943 |
| 21-Sep-2024 |
Kazu Hirata <kazu@google.com> |
[AMDGPU] Avoid repeated hash lookups (NFC) (#109506)
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Revision tags: llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3 |
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05b75e00 |
| 12-Aug-2024 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
AMDGPU/NewPM: Port AMDGPULateCodeGenPrepare to new pass manager (#102806)
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Revision tags: llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init |
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03936534 |
| 22-Jul-2024 |
Jeffrey Byrnes <Jeffrey.Byrnes@amd.com> |
[AMDGPU] Protect against null entries in ValMap
Change-Id: Icbda7c3fecf38679d06006986e5e17cb1f1b8749
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6e68b75e |
| 16-Jul-2024 |
Jeffrey Byrnes <Jeffrey.Byrnes@amd.com> |
[AMDGPU] Reland: Do not use original PHIs in coercion chains
Change-Id: I579b5c69a85997f168ed35354b326524b6f84ef7
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| #
1612e4a3 |
| 15-Jul-2024 |
Jay Foad <jay.foad@amd.com> |
Revert "[AMDGPU] Do not use original PHIs in coercion chains (#98063)"
This reverts commit dc8ea046a516c3bdd0ece306f406c9ea833d4dac.
It generated broken IR as described here:
https://github.com/llv
Revert "[AMDGPU] Do not use original PHIs in coercion chains (#98063)"
This reverts commit dc8ea046a516c3bdd0ece306f406c9ea833d4dac.
It generated broken IR as described here:
https://github.com/llvm/llvm-project/pull/98063#issuecomment-2225259451
show more ...
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| #
dc8ea046 |
| 10-Jul-2024 |
Jeffrey Byrnes <jeffrey.byrnes@amd.com> |
[AMDGPU] Do not use original PHIs in coercion chains (#98063)
It's possible that we are unable to coerce all the incoming values of a
PHINode (A). Thus, we are unable to coerce the PHINode. In this
[AMDGPU] Do not use original PHIs in coercion chains (#98063)
It's possible that we are unable to coerce all the incoming values of a
PHINode (A). Thus, we are unable to coerce the PHINode. In this
situation, we previously would add the PHINode back to the ValMap. This
would cause a problem is PhiNode (B) was a user of A. In this scenario,
if B has been coerced, we would hit an assert regarding the incompatible
type between the PHINode and its incoming value.
Deleting non-coerced PHINodes from the map, and propagating the removal
to users, resolves the issue.
show more ...
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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0 |
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5da7179c |
| 14-Sep-2023 |
Jeffrey Byrnes <Jeffrey.Byrnes@amd.com> |
[AMDGPU] Reland: Add IR LiveReg type-based optimization
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3e53c97d |
| 29-Jun-2024 |
Vitaly Buka <vitalybuka@google.com> |
Revert "[AMDGPU] Add IR LiveReg type-based optimization" (#97138)
Part of #66838.
https://lab.llvm.org/buildbot/#/builders/52/builds/404
https://lab.llvm.org/buildbot/#/builders/55/builds/358
h
Revert "[AMDGPU] Add IR LiveReg type-based optimization" (#97138)
Part of #66838.
https://lab.llvm.org/buildbot/#/builders/52/builds/404
https://lab.llvm.org/buildbot/#/builders/55/builds/358
https://lab.llvm.org/buildbot/#/builders/164/builds/518
This reverts commit ded956440739ae326a99cbaef18ce4362e972679.
show more ...
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| #
ded95644 |
| 14-Sep-2023 |
Jeffrey Byrnes <Jeffrey.Byrnes@amd.com> |
[AMDGPU] Add IR LiveReg type-based optimization
Change-Id: Ia0d11b79b8302e79247fe193ccabc0dad2d359a0
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89226ecb |
| 19-Jan-2024 |
Jay Foad <jay.foad@amd.com> |
[AMDGPU] Do not widen scalar loads on GFX12 (#78724)
GFX12 has subword scalar loads so there is no need to do this.
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4a774146 |
| 17-Jan-2024 |
Jay Foad <jay.foad@amd.com> |
[AMDGPU] CodeGen for GFX12 8/16-bit SMEM loads (#77633)
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Revision tags: llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3 |
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3e16167c |
| 29-Apr-2023 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
AMDGPU: Use getTypeStoreSizeInBits
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4202ad5d |
| 29-Apr-2023 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
AMDGPU: Don't create a pointer bitcast in AMDGPULateCodeGenPrepare
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Revision tags: llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4 |
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036431e3 |
| 06-Mar-2023 |
pvanhout <pierre.vanhoutryve@amd.com> |
[AMDGPU] Use UniformityAnalysis in LateCodeGenPrepare
Reviewed By: foad
Differential Revision: https://reviews.llvm.org/D145366
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Revision tags: llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2, llvmorg-13.0.1-rc1 |
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| #
4bef0304 |
| 03-Nov-2021 |
Kazu Hirata <kazu@google.com> |
[AArch64, AMDGPU] Use make_early_inc_range (NFC)
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Revision tags: llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init |
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| #
357756ec |
| 17-Jul-2021 |
Nikita Popov <nikita.ppv@gmail.com> |
[OpaquePtr] Remove uses of CreateConstGEP1_64() without element type
Remove uses of to-be-deprecated API.
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Revision tags: llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1 |
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| #
a15ed701 |
| 11-May-2021 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
AMDGPU: Fix assert on constant load from addrspacecasted pointer
This was trying to create a bitcast between different address spaces.
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Revision tags: llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2 |
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| #
46354bac |
| 11-Feb-2021 |
Nikita Popov <nikita.ppv@gmail.com> |
[OpaquePtrs] Remove some uses of type-less CreateLoad APIs (NFC)
Explicitly pass loaded type when creating loads, in preparation
for the deprecation of these APIs.
There are still a couple of uses
[OpaquePtrs] Remove some uses of type-less CreateLoad APIs (NFC)
Explicitly pass loaded type when creating loads, in preparation
for the deprecation of these APIs.
There are still a couple of uses left.
show more ...
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Revision tags: llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2, llvmorg-11.1.0-rc1 |
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| #
6a87e9b0 |
| 25-Dec-2020 |
dfukalov <daniil.fukalov@amd.com> |
[NFC][AMDGPU] Reduce include files dependency.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D93813
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