[JITLink][RISCV] Implement eh_frame handling (#68253)

This requires adding a `NegDelta32` edge kind that cannot be mapped to
existing relocations.

Co-authored-by: Job Noorman <jnoorman@igalia.co

[JITLink][RISCV] Implement eh_frame handling (#68253)

This requires adding a `NegDelta32` edge kind that cannot be mapped to
existing relocations.

Co-authored-by: Job Noorman <jnoorman@igalia.com>

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[JITLink][RISCV] Implement linker relaxation

This patch is essentially an adaption of LLD's algorithm to JITLink.
Currently, only relaxing R_RISCV_CALL(_PLT) and R_RISCV_ALIGN is
implemented, other

[JITLink][RISCV] Implement linker relaxation

This patch is essentially an adaption of LLD's algorithm to JITLink.
Currently, only relaxing R_RISCV_CALL(_PLT) and R_RISCV_ALIGN is
implemented, other relocations can follow later.

From a high level, the algorithm works as follows. In the first phase
(relaxBlock), we iteratively try to relax all instructions that have a
R_RISCV_RELAX relocation:
- If, based on the current symbol values, an instruction sequence can be
relaxed (i.e., replaced by a shorter instruction), we record how many
bytes would be removed, the new instruction (Writes), and the new
relocation type (EdgeKinds).
- We keep track of the total number of bytes that got removed up to each
relocation in the RelocDeltas array. This is the cumulative sum of the
number of bytes removed for each relocation.
- Symbol values and sizes are updated based on the number of removed
bytes.
- If for any relocation, the current RelocDeltas value doesn't match the
one from the previous iteration, something changed and we need to run
another iteration as some symbols might now have different values.

In the second phase (finalizeBlockRelax), all code is moved based on
RelocDeltas, the relaxed instructions are rewritten using Writes, and
R_RISCV_ALIGN is handled (moving instructions to ensure alignment and
inserting the correct NOP-sequence if needed). Finally, edge kinds and
offsets are updated and all R_RISCV_RELAX and R_RISCV_ALIGN edges are
removed (they are not needed anymore for the fixup linking stage).

Linker relaxation is implemented as a pass and added to PreFixupPasses
in the default configuration on RISC-V.

Since linker relaxation removes instructions, the memory for blocks
should ideally be reallocated. However, I believe this is currently not
possible in JITLink. Therefore, relaxation directly modifies the memory
of blocks, reducing the number of instructions but not the size of
blocks. I'm not very familiar with JITLink's memory allocators so I
might be overlooking something here, though.

Note on testing: some of the tests rely on the debug output of
llvm-jitlink. The main reason for this is the verification of symbol
sizes (which may change due to relaxation). I don't believe this can be
done using jitlink-check checks alone.

Note that there is a slightly unrelated change that makes
Symbol::setOffset public to be able to update symbol offsets during
relaxation.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D149526

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[JITLink][RISCV] Add R_RISCV_RVC_BRANCH and R_RISCV_RVC_JUMP

These are the compressed equivalents of the relocations R_RISCV_BRANCH
and R_RISCV_JAL with slightly more complex immediate handling.

Di

[JITLink][RISCV] Add R_RISCV_RVC_BRANCH and R_RISCV_RVC_JUMP

These are the compressed equivalents of the relocations R_RISCV_BRANCH
and R_RISCV_JAL with slightly more complex immediate handling.

Differential Revision: https://reviews.llvm.org/D140827

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[JITLink][RISCV] Order EdgeKind_riscv the same way as relocations

There were basically four different orderings: one defined by the
relocations, one by the enum definition of EdgeKind_riscv, one for

[JITLink][RISCV] Order EdgeKind_riscv the same way as relocations

There were basically four different orderings: one defined by the
relocations, one by the enum definition of EdgeKind_riscv, one for
mapping the enum values to their names, and one when mapping the
relocations to edge kinds and finally processing them. Chose the
ordering defined by the relocations in the riscv-elf-psabi-doc as
the canonical one.

Differential Revision: https://reviews.llvm.org/D140802

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[JITLink][RISCV] Add R_RISCV_LO12_S relocation support

Fixes: https://github.com/llvm/llvm-project/issues/58979

Reviewed By: Hahnfeld

Differential Revision: https://reviews.llvm.org/D138030

[JITLink][RISCV] Add names for GOT/PLT relocations

It is confusing to see "Unrecognized edge kind" in debugging output
for supported relocations; this was probably an oversight in commit
89f546f6ba

[JITLink][RISCV] Add names for GOT/PLT relocations

It is confusing to see "Unrecognized edge kind" in debugging output
for supported relocations; this was probably an oversight in commit
89f546f6ba which added the support.

Differential Revision: https://reviews.llvm.org/D136985

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[JITLink] Add R_RISCV_SUB6 relocation

Add R_RISCV_SUB6 relocation

Differential Revision: https://reviews.llvm.org/D120001

[JITLink][RISCV] fix the extractBits behavior and add R_RISCV_JAL relocation.

This patch supports the R_RISCV_JAL relocation.
Moreover, it will fix the extractBits function's behavior as it extracts

[JITLink][RISCV] fix the extractBits behavior and add R_RISCV_JAL relocation.

This patch supports the R_RISCV_JAL relocation.
Moreover, it will fix the extractBits function's behavior as it extracts Size + 1 bits.
In the test ELF_jal.s:
Before:
```
Hi: 4294836480
extractBits(Hi, 12, 8): 480
```
After:
```
Hi: 4294836480
extractBits(Hi, 12, 8): 224
```

Reviewed By: StephenFan

Differential Revision: https://reviews.llvm.org/D117975

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Revert "[JITLink][RISCV] fix the extractBits behavior and add R_RISCV_JAL relocation."

This reverts commit 3af7bbca4a0ef64de64b8bb38d3b167673ec60f0.

[JITLink][RISCV] fix the extractBits behavior and add R_RISCV_JAL relocation.

This patch supports the R_RISCV_JAL relocation.
Moreover, it will fix the extractBits function's behavior as it extracts

[JITLink][RISCV] fix the extractBits behavior and add R_RISCV_JAL relocation.

This patch supports the R_RISCV_JAL relocation.
Moreover, it will fix the extractBits function's behavior as it extracts Size + 1 bits.
In the test ELF_jal.s:
Before:
```
Hi: 4294836480
extractBits(Hi, 12, 8): 480
```
After:
```
Hi: 4294836480
extractBits(Hi, 12, 8): 224
```

Reviewed By: StephenFan

Differential Revision: https://reviews.llvm.org/D117975

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reapply de872382951 "[JITLink] Add anonymous symbols in LinkGraph..."
with fixes

This reapply `de872382951572b70dfaefe8d77eb98d15586115`, which was
reverted in `fdb6578514dd3799ad23c8bbb7699577c0fb4

reapply de872382951 "[JITLink] Add anonymous symbols in LinkGraph..."
with fixes

This reapply `de872382951572b70dfaefe8d77eb98d15586115`, which was
reverted in `fdb6578514dd3799ad23c8bbb7699577c0fb414d`

Add `# REQUIRES: asserts` in test file `anonymous_symbol.s` to disable
this test for non-debug build

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[JITLink][RISCV] Support R_RISCV_SET* and R_RISCV_32_PCREL relocations

This patch supports R_RISCV_SET* and R_RISCV_32_PCREL relocations in JITLink.

Reviewed By: StephenFan

Differential Revision:

[JITLink][RISCV] Support R_RISCV_SET* and R_RISCV_32_PCREL relocations

This patch supports R_RISCV_SET* and R_RISCV_32_PCREL relocations in JITLink.

Reviewed By: StephenFan

Differential Revision: https://reviews.llvm.org/D117082

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Revert "[JITLink] Add anonymous symbols in LinkGraph for unnamed temporary symbols"

This reverts commit de872382951572b70dfaefe8d77eb98d15586115.

Buildbot check error

[JITLink] Add anonymous symbols in LinkGraph for unnamed temporary symbols

In RISCV, temporary symbols will be used to generate dwarf, eh_frame sections..., and will be placed in object code's symbo

[JITLink] Add anonymous symbols in LinkGraph for unnamed temporary symbols

In RISCV, temporary symbols will be used to generate dwarf, eh_frame sections..., and will be placed in object code's symbol table. However, LLVM does not use names on these temporary symbols. This patch add anonymous symbols in LinkGraph for these temporary symbols.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D116475

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[JITLink] Add RISCV label subtraction and addition relocations

This patch add RISCV label subtraction and addition relocations in JITLink

Differential Revision: https://reviews.llvm.org/D116794

[jitlink] add R_RISCV_BRANCH to jitlink

This patch supported the R_RISCV_BRANCH relocation.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D116573

[JITLink] Add riscv.cpp