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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4 |
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549413fa |
| 16-Nov-2024 |
David Green <david.green@arm.com> |
[AArch64][GlobalISel] Protect against folding loads across basic blocks.
isObviouslySafeToFold can look between a load and an instruction it can be
folded into, to check that no other memory operati
[AArch64][GlobalISel] Protect against folding loads across basic blocks.
isObviouslySafeToFold can look between a load and an instruction it can be
folded into, to check that no other memory operations prevents the fold. It
doesn't handle multiple basic blocks which we needs to guard against.
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Revision tags: llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4 |
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d58bd211 |
| 27-Aug-2024 |
chuongg3 <chuong.goh@arm.com> |
[GlobalISel] Look between instructions to be matched (#101675)
When a pattern is matched in TableGen, a check is run called
isObviouslySafeToFold(). One of the condition that it checks for is
whet
[GlobalISel] Look between instructions to be matched (#101675)
When a pattern is matched in TableGen, a check is run called
isObviouslySafeToFold(). One of the condition that it checks for is
whether the instructions that are being matched are consecutive, so the
instruction's insertion point does not change.
This patch allows the movement of the insertion point of a load
instruction if none of the intervening instructions are stores or have
side-effects.
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Revision tags: llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init |
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| #
63afb705 |
| 25-Jul-2023 |
pvanhout <pierre.vanhoutryve@amd.com> |
[RFC][GlobalISel] Overhauled MIR Patterns Support for Combiners
See https://discourse.llvm.org/t/rfc-overhauled-mir-patterns-for-globalisel-combiners/72264
This is a complete overrhaul of the recen
[RFC][GlobalISel] Overhauled MIR Patterns Support for Combiners
See https://discourse.llvm.org/t/rfc-overhauled-mir-patterns-for-globalisel-combiners/72264
This is a complete overrhaul of the recently-added GlobalISel Match Table backend which adds
support for MIR patterns for both match and apply patterns.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D156315
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1fe7d9c7 |
| 26-Jun-2023 |
pvanhout <pierre.vanhoutryve@amd.com> |
[GlobalISel] Generalize `InstructionSelector` Match Tables
Makes `InstructionSelector.h`/`InstructionSelectorImpl.h` generic so the match tables can also be used for the combiner.
Some notes:
- Co
[GlobalISel] Generalize `InstructionSelector` Match Tables
Makes `InstructionSelector.h`/`InstructionSelectorImpl.h` generic so the match tables can also be used for the combiner.
Some notes:
- Coverage was made an optional parameter of `executeMatchTable`, combines won't use it for now.
- `GIPFP_` -> `GICXXPred_` so it's more generic. Those are just C++ predicates and aren't PatFrag-specific.
- Pass the MatcherState directly to testMIPredicate_MI, the combiner will need it.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D153755
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