[MC] Use MCRegister and remove implicit casts from MCRegister to unsigned. NFC

[NFC] Update function names in MCTargetAsmParser.h (#108643)

Update function names to adhere to LLVM coding standard.

[MC] Make `MCParsedAsmOperand::getReg()` return `MCRegister` (#86444)

[ARM,MC] Support FDPIC relocations

Linux kernel fs/binfmt_elf_fdpic.c supports FDPIC for MMU-less systems.
GCC/binutils/qemu support FDPIC ABI for ARM
(https://github.com/mickael-guene/fdpic_doc).
_

[ARM,MC] Support FDPIC relocations

Linux kernel fs/binfmt_elf_fdpic.c supports FDPIC for MMU-less systems.
GCC/binutils/qemu support FDPIC ABI for ARM
(https://github.com/mickael-guene/fdpic_doc).
_ARM FDPIC Toolchain and ABI_ provides a summary.

This patch implements FDPIC relocations to the integrated assembler.
There are 6 static relocations and 2 dynamic relocations, with
R_ARM_FUNCDESC as both static and dynamic.

gas requires `--fdpic` to assemble data relocations like `.word f(FUNCDESC)`.
This patch adds `MCTargetOptions::FDPIC` and reports an error if FDPIC
is not set.

Pull Request: https://github.com/llvm/llvm-project/pull/82187

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[MC] Change tryParseRegister to return ParseStatus (NFC)

This finishes the work of replacing OperandMatchResultTy with
ParseStatus, started in D154101.
As a drive-by change, rename some RegNo variab

[MC] Change tryParseRegister to return ParseStatus (NFC)

This finishes the work of replacing OperandMatchResultTy with
ParseStatus, started in D154101.
As a drive-by change, rename some RegNo variables to just Reg
(a leftover from the days when RegNo had 'unsigned' type).

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[MC] Use ParseStatus in generated AsmParser methods

ParseStatus is slightly more convenient to use due to implicit
conversion from bool, which allows to do something like:
```
return Error(L, "msg

[MC] Use ParseStatus in generated AsmParser methods

ParseStatus is slightly more convenient to use due to implicit
conversion from bool, which allows to do something like:
```
return Error(L, "msg");
```
when with MatchOperandResultTy it had to be:
```
Error(L, "msg");
return MatchOperand_ParseFail;
```
It also has more appropriate name since parse* methods are not only for
parsing operands.

Reviewed By: kosarev

Differential Revision: https://reviews.llvm.org/D154303

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Revert "[MC] Allow conversion between ParseStatus and MatchOperandResultTy"

This reverts commit 15ef9b26adeb8c9dd98228fc26757966d8355986.

Going to put it for review with larger set of differences.

[MC] Allow conversion between ParseStatus and MatchOperandResultTy

This allows a smooth transition to ParseStatus.

[MC] Add three-state parseDirective as a replacement for ParseDirective

Conventionally, parsing methods return false on success and true on
error. However, directive parsing methods need a third sta

[MC] Add three-state parseDirective as a replacement for ParseDirective

Conventionally, parsing methods return false on success and true on
error. However, directive parsing methods need a third state: the
directive is not target specific. AsmParser::parseStatement detected
this case by using a fragile heuristic: if the target parser did not
consume any tokens, the directive is assumed to be not target-specific.

Some targets fail to follow the convention: they return success after
emitting an error or do not consume the entire line and return failure
on successful parsing. This was partially worked around by checking for
pending errors in parseStatement.

This patch tries to improve the situation by introducing parseDirective
method that returns ParseStatus -- three-state class. The new method
should eventually replace the old one returning bool.

ParseStatus is intentionally implicitly constructible from bool to allow
uses like `return Error(Loc, "message")`. It also has a potential to
replace OperandMatchResulTy as it is more convenient to use due to the
implicit construction from bool and more type safe.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D154101

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Move SubtargetFeature.h from MC to TargetParser

SubtargetFeature.h is currently part of MC while it doesn't depend on
anything in MC. Since some LLVM components might have the need to work
with targ

Move SubtargetFeature.h from MC to TargetParser

SubtargetFeature.h is currently part of MC while it doesn't depend on
anything in MC. Since some LLVM components might have the need to work
with target features without necessarily needing MC, it might be
worthwhile to move SubtargetFeature.h to a different location. This will
reduce the dependencies of said components.

Note that I choose TargetParser as the destination because that's where
Triple lives and SubtargetFeatures feels related to that.

This issues came up during a JITLink review (D149522). JITLink would
like to avoid a dependency on MC while still needing to store target
features.

Reviewed By: MaskRay, arsenm

Differential Revision: https://reviews.llvm.org/D150549

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[MCParser] Modernize IntelExpr (NFC)

Identified with readability-redundant-member-init.

[MC] Use MCRegister instead of unsigned in MCInstPrinter (NFC)

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D140654

[MC] Use `MCRegister` instead of `unsigned` in `MCTargetAsmParser`

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D140273

[AArch64]SME2 Multi-single vector SVE Destructive 2 and 4 Registers

This patch adds the assembly/disassembly for the following instructions:
ADD (to vector): Add replicated single vector to multi-

[AArch64]SME2 Multi-single vector SVE Destructive 2 and 4 Registers

This patch adds the assembly/disassembly for the following instructions:
ADD (to vector): Add replicated single vector to multi-vector with multi-vector result.
SQDMULH (multiple and single vector): Multi-vector signed saturating doubling multiply high by vector.
for 2 and 4 ZA SVE registers.

The reference can be found here:

https://developer.arm.com/documentation/ddi0602/2022-09

It also adds more size for the multiple register tuple:
ZZ_b_mul_r, ZZ_h_mul_r,
ZZZZ_b_mul_r, ZZZZ_h_mul_r,
for 8 bits and 16 bits with 2 and 4 ZA registers.

Depends on: D135468

With a fix for Mips for this test:
llvm/test/MC/Mips/mips64r6/valid.s

Differential Revision: https://reviews.llvm.org/D135563

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Revert "[AArch64]SME2 Multi-single vector SVE Destructive 2 and 4 Registers"

This reverts commit 4c4909703d74883e5cc49edcbd22b783135d2897.

This patch was breaking this test:

llvm/test/MC/Mips/mips

Revert "[AArch64]SME2 Multi-single vector SVE Destructive 2 and 4 Registers"

This reverts commit 4c4909703d74883e5cc49edcbd22b783135d2897.

This patch was breaking this test:

llvm/test/MC/Mips/mips64r6/valid.s

I will push again when fixed

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[AArch64]SME2 Multi-single vector SVE Destructive 2 and 4 Registers

This patch adds the assembly/disassembly for the following instructions:
ADD (to vector): Add replicated single vector to multi-

[AArch64]SME2 Multi-single vector SVE Destructive 2 and 4 Registers

This patch adds the assembly/disassembly for the following instructions:
ADD (to vector): Add replicated single vector to multi-vector with multi-vector result.
SQDMULH (multiple and single vector): Multi-vector signed saturating doubling multiply high by vector.
for 2 and 4 ZA SVE registers.

The reference can be found here:

https://developer.arm.com/documentation/ddi0602/2022-09

It also adds more size for the multiple register tuple:
ZZ_b_mul_r, ZZ_h_mul_r,
ZZZZ_b_mul_r, ZZZZ_h_mul_r,
for 8 bits and 16 bits with 2 and 4 ZA registers.

Depends on: D135468

Differential Revision: https://reviews.llvm.org/D135563

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[MC][WebAssembly] Allow accurate errors in doBeforeLabelEmit

Although we only currently have one error produced in this function I am
working on changes right now that add some more. This change ma

[MC][WebAssembly] Allow accurate errors in doBeforeLabelEmit

Although we only currently have one error produced in this function I am
working on changes right now that add some more. This change makes the
error location more accurate.

Differential Revision: https://reviews.llvm.org/D133016

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[InlineAsm] Fix mangle problem when global variable used in inline asm
(Add modifier P for ARR[BaseReg+IndexReg+..])

Reviewed By: skan

Differential Revision: https://reviews.llvm.org/D120887

Cleanup MCParser headers

As usual with that header cleanup series, some implicit dependencies now need to
be explicit:

llvm/MC/MCParser/MCAsmParser.h no longer includes llvm/MC/MCParser/MCAsmLexer.

Cleanup MCParser headers

As usual with that header cleanup series, some implicit dependencies now need to
be explicit:

llvm/MC/MCParser/MCAsmParser.h no longer includes llvm/MC/MCParser/MCAsmLexer.h

Preprocessed lines to build llvm on my setup:
after: 1068185081
before: 1068324320

So no compile time benefit to expect, but we still get the looser coupling
between files which is great.

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D119359

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Revert "[llvm] Remove redundant member initialization (NFC)"

This reverts commit fd4808887ee47f3ec8a030e9211169ef4fb094c3.

This patch causes gcc to issue a lot of warnings like:

warning: base cl

Revert "[llvm] Remove redundant member initialization (NFC)"

This reverts commit fd4808887ee47f3ec8a030e9211169ef4fb094c3.

This patch causes gcc to issue a lot of warnings like:

warning: base class ‘class llvm::MCParsedAsmOperand’ should be
explicitly initialized in the copy constructor [-Wextra]

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[llvm] Remove redundant member initialization (NFC)

Identified with readability-redundant-member-init.

AMDGPU: Add target id and code object v4 support

- Add target id support (https://clang.llvm.org/docs/ClangOffloadBundler.html#target-id)
- Add code object v4 support (https://llvm.org/docs/AMDG

AMDGPU: Add target id and code object v4 support

- Add target id support (https://clang.llvm.org/docs/ClangOffloadBundler.html#target-id)
- Add code object v4 support (https://llvm.org/docs/AMDGPUUsage.html#elf-code-object)
- Add kernarg_size to kernel descriptor
- Change trap handler ABI to no longer move queue pointer into s[0:1]
- Cleanup ELF definitions
- Add V2, V3, V4 suffixes to make a clear distinction for code object version
- Consolidate note names

Differential Revision: https://reviews.llvm.org/D95638

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Remove unnecessary forward declarations. NFCI.

All of these forward declarations are fully defined in headers that are directly included.

[ms] [llvm-ml] Add support for size queries in MASM

Add support for size inference, sizeof, typeof, and lengthof.

Reviewed By: thakis

Differential Revision: https://reviews.llvm.org/D86947

[ms] [llvm-ml] Add initial MASM STRUCT/UNION support

Summary:
Add support for user-defined types to MasmParser, including initialization and field access.

Known issues:
- Omitted entry initializers

[ms] [llvm-ml] Add initial MASM STRUCT/UNION support

Summary:
Add support for user-defined types to MasmParser, including initialization and field access.

Known issues:
- Omitted entry initializers (e.g., <,0>) do not work consistently for nested structs/arrays.
- Size checking/inference for values with known types is not yet implemented.
- Some ml64.exe syntaxes for accessing STRUCT fields are not recognized.
- `[<register>.<struct name>].<field>`
- `[<register>[<struct name>.<field>]]`
- `(<struct name> PTR [<register>]).<field>`
- `[<variable>.<struct name>].<field>`
- `(<struct name> PTR <variable>).<field>`

Reviewed By: thakis

Differential Revision: https://reviews.llvm.org/D75306

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