TargetLibraryInfo: Use pointer index size to determine getSizeTSize(). (#118747)

When using non-integral pointer types, such as on CHERI targets, size_t
is equivalent
to the index size, which is a

TargetLibraryInfo: Use pointer index size to determine getSizeTSize(). (#118747)

When using non-integral pointer types, such as on CHERI targets, size_t
is equivalent
to the index size, which is allowed to be smaller than the size of the
pointer.

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[Analysis] atan2: isTriviallyVectorizable; add to massv and accelerate veclibs (#113637)

This change is part of this proposal:
https://discourse.llvm.org/t/rfc-all-the-math-intrinsics/78294

- Re

[Analysis] atan2: isTriviallyVectorizable; add to massv and accelerate veclibs (#113637)

This change is part of this proposal:
https://discourse.llvm.org/t/rfc-all-the-math-intrinsics/78294

- Return true for atan2 from isTriviallyVectorizable
- Add atan2 to VecFuncs.def for massv and accelerate libraries.
- Add atan2 to hasOptimizedCodeGen
- Add atan2 support in llvm/lib/Analysis/ValueTracking.cpp
llvm::getIntrinsicForCallSite and update vectorization tests
- Add atan2 name check to isLoweredToCall in
llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
- Note: there's no test coverage for these names in isLoweredToCall, except that Transforms/TailCallElim/inf-recursion.ll is impacted by the "fabs" case

Thanks to @jroelofs for the atan2 accelerate veclib and associated test
additions, plus the hasOptimizedCodeGen addition.

Part of: Implement the atan2 HLSL Function #70096.

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Adding more vector calls for -fveclib=AMDLIBM (#109662)

AMD has it's own implementation of vector calls.
New vector calls are introduced in the library for exp10, log10, sincos and finite asin/acos

Adding more vector calls for -fveclib=AMDLIBM (#109662)

AMD has it's own implementation of vector calls.
New vector calls are introduced in the library for exp10, log10, sincos and finite asin/acos
Please refer [https://github.com/amd/aocl-libm-ose]

---------

Co-authored-by: Rohit Aggarwal <Rohit.Aggarwal@amd.com>

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[llvm][TLI] Sort a switch's cases. NFC

[Analysis] getIntrinsicForCallSite - add vectorization support for acos/asin/atan and cosh/sinh/tanh libcalls (#106844)

Followup to #106584 - ensure acos/asin/atan and cosh/sinh/tanh libcalls correc

[Analysis] getIntrinsicForCallSite - add vectorization support for acos/asin/atan and cosh/sinh/tanh libcalls (#106844)

Followup to #106584 - ensure acos/asin/atan and cosh/sinh/tanh libcalls correctly map to the llvm intrinsic equivalents

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[NFC] Cleanup in ADT and Analysis headers. (#104484)

Remove unused directly includes and forward declarations in ADT and
Analysis headers.

[Analysis][NFC] Don't use BitVector for nobuiltin overrides

Avoid one heap allocation per function per constructed TLI. The
BitVector is never resized, so a bitset is sufficient.

Pull Request: http

[Analysis][NFC] Don't use BitVector for nobuiltin overrides

Avoid one heap allocation per function per constructed TLI. The
BitVector is never resized, so a bitset is sufficient.

Pull Request: https://github.com/llvm/llvm-project/pull/103411

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[Analysis] Use BitVector::test in areInlineCompatible (NFC) (#98776)

areInlineCompatible checks to see if CalleeTLI.OverrideAsUnavailable
is a subset of OverrideAsUnavailable by computing a union o

[Analysis] Use BitVector::test in areInlineCompatible (NFC) (#98776)

areInlineCompatible checks to see if CalleeTLI.OverrideAsUnavailable
is a subset of OverrideAsUnavailable by computing a union of the two
and comparing the union and OverrideAsUnavailable.

The problem is that computing a union involves memory allocations.
This patch removes the need for memory allocations by switching to
BitVector::test. Note that A.test(B) returns true if A - B is
non-empty. That is, !A.test(B) is true if A if a subset of B.

The use of BitVector::test here saves 0.20% of heap allocations during
the compilation of X86ISelLowering.cpp.ii, a preprocessed version of
X86ISelLowering.cpp.

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[SLPVectorizer] Support SLPVectorizer cases of tan across all backends (#95517)

This PR is intended to address the limited SLPVectorizer support of tan
raised in the comments of this PR:
https://g

[SLPVectorizer] Support SLPVectorizer cases of tan across all backends (#95517)

This PR is intended to address the limited SLPVectorizer support of tan
raised in the comments of this PR:
https://github.com/llvm/llvm-project/pull/94559.

Right now emitting the tan intrinsisic allows you to vectorize tan, but
emitting the libfunc does not. to address this the libcall needs to be
mapped to the intrinsic. and the libcall and function name need to be
marked approriately so they can be optimized or defined as a call
lowering.

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[TargetLibraryInfo] Use the default move constructor/assignment operator (#95685)

commit ecea8371ff03c15fb3dc27ee4108b98335fd2d63
Author: Kazu Hirata <kazu@google.com>
Date: Sat Jun 15 14:02

[TargetLibraryInfo] Use the default move constructor/assignment operator (#95685)

commit ecea8371ff03c15fb3dc27ee4108b98335fd2d63
Author: Kazu Hirata <kazu@google.com>
Date: Sat Jun 15 14:02:42 2024 -0700

added std::move to the move constructor and assignment operator, but
we can just use = default to have the compiler to generate them.

As expected, the number of heap allocations is virtually unchanged.

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[TargetLibraryInfo] Use std::move (NFC) (#95671)

The std::move here saves 0.11% of heap allocations during the
compilation of a large preprocessed file, namely X86ISelLowering.cpp,
for the X86 tar

[TargetLibraryInfo] Use std::move (NFC) (#95671)

The std::move here saves 0.11% of heap allocations during the
compilation of a large preprocessed file, namely X86ISelLowering.cpp,
for the X86 target.

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PlaceSafepoints: Fix using default constructed TargetLibraryInfo (#92411)

Adding support of AMDLIBM vector library (#78560)

Hi,

AMD has it's own implementation of vector calls. This patch include the
changes to enable the use of AMD's math library using -fveclib=AMDLI

Adding support of AMDLIBM vector library (#78560)

Hi,

AMD has it's own implementation of vector calls. This patch include the
changes to enable the use of AMD's math library using -fveclib=AMDLIBM.
Please refer https://github.com/amd/aocl-libm-ose

---------

Co-authored-by: Rohit Aggarwal <Rohit.Aggarwal@amd.com>

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[TLI] Add getLibFunc that accepts an Opcode and scalar Type. (#75919)

It sets a LibFunc similarly with the other two getLibFunc methods.
Currently, it supports only the FRem Instruction.

Add tes

[TLI] Add getLibFunc that accepts an Opcode and scalar Type. (#75919)

It sets a LibFunc similarly with the other two getLibFunc methods.
Currently, it supports only the FRem Instruction.

Add tests for FRem.

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Fix mechanism propagating mangled names for TLI function mappings (#66656)

Currently the mappings from TLI are used to generate the list of
available "scalar to vector" mappings attached to scalar

Fix mechanism propagating mangled names for TLI function mappings (#66656)

Currently the mappings from TLI are used to generate the list of
available "scalar to vector" mappings attached to scalar calls as
"vector-function-abi-variant" LLVM IR attribute. Function names from TLI
are wrapped in mangled name following the pattern:
_ZGV<isa><mask><vlen><parameters>_<scalar_name>[(<vector_redirection>)]
The problem is the mangled name uses _LLVM_ as the ISA name which
prevents the compiler to compute vectorization factor for scalable
vectors as it cannot make any decision based on the _LLVM_ ISA. If we
use "s" as the ISA name, the compiler can make decisions based on VFABI
specification where SVE spacific rules are described.

This patch is only a refactoring stage where there is no change to the
compiler's behaviour.

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[TLI][AArch64] Add mappings to vectorized functions from ArmPL

Arm Performance Libraries contain math library which provides
vectorized versions of common math functions.
This patch allows to use it

[TLI][AArch64] Add mappings to vectorized functions from ArmPL

Arm Performance Libraries contain math library which provides
vectorized versions of common math functions.
This patch allows to use it with clang and llvm via -fveclib=ArmPL or
-vector-library=ArmPL, so loops with such calls can be vectorized.
The executable needs to be linked with the amath library.

Arm Performance Libraries are available at:
https://developer.arm.com/Tools%20and%20Software/Arm%20Performance%20Libraries

Reviewed by: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D154508

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IR: Add llvm.ldexp and llvm.experimental.constrained.ldexp intrinsics

AMDGPU has native instructions and target intrinsics for this, but
these really should be subject to legalization and generic
op

IR: Add llvm.ldexp and llvm.experimental.constrained.ldexp intrinsics

AMDGPU has native instructions and target intrinsics for this, but
these really should be subject to legalization and generic
optimizations. This will enable legalization of f16->f32 on targets
without f16 support.

Implement a somewhat horrible inline expansion for targets without
libcall support. This could be better if we could introduce control
flow (GlobalISel version not yet implemented). Support for strictfp
legalization is less complete but works for the simple cases.

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[Analysis][LoongArch] Add sign extension for i32 parameters and returns

In LoongArch ABI spec, we can see that in the LP64D ABI, unsigned 32-bit
types, such as unsigned int, are stored in general-pu

[Analysis][LoongArch] Add sign extension for i32 parameters and returns

In LoongArch ABI spec, we can see that in the LP64D ABI, unsigned 32-bit
types, such as unsigned int, are stored in general-purpose registers as
proper sign extensions of their 32-bit values.

Reference:
https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html#_abi_lp64d

Reviewed By: SixWeining, xen0n

Differential Revision: https://reviews.llvm.org/D151794

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[TLI][AArch64] Extend SLEEF vectorized functions mapping with VLA functions

This commit extends D134719 "[AArch64] Enable libm vectorized
functions via SLEEF" with the mappings for the scalable func

[TLI][AArch64] Extend SLEEF vectorized functions mapping with VLA functions

This commit extends D134719 "[AArch64] Enable libm vectorized
functions via SLEEF" with the mappings for the scalable functions.

It also introduces all the necessary changes needed to support masked
interfaces.

Reviewed By: danielkiss, sdesmalen

Differential Revision: https://reviews.llvm.org/D146839

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Revert "[TLI][AArch64] Extend SLEEF vectorized functions mapping with VLA functions"

Reverting it so I could land it with Arcanist.

This reverts commit 59dcf927ee43e995374907b6846b657f68d7ea49.

[TLI][AArch64] Extend SLEEF vectorized functions mapping with VLA functions

This commit extends D134719 "[AArch64] Enable libm vectorized
functions via SLEEF" with the mappings for the scalable func

[TLI][AArch64] Extend SLEEF vectorized functions mapping with VLA functions

This commit extends D134719 "[AArch64] Enable libm vectorized
functions via SLEEF" with the mappings for the scalable functions.

It also introduces all the necessary changes needed to support masked
interfaces.

Signed-off-by: Paul Osmialowski <pawel.osmialowski@arm.com>

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[llvm] Use *{Map,Set}::contains (NFC)

[NFC][TargetParser] Remove llvm/ADT/Triple.h

I also ran `git clang-format` to get the headers in the right order for
the new location, which has changed the order of other headers in two
files.

[AArch64] Enable libm vectorized functions via SLEEF

It enables trigonometry functions vectorization via SLEEF: http://sleef.org/.

- A new vectorization library enum is added to TargetLibraryInfo

[AArch64] Enable libm vectorized functions via SLEEF

It enables trigonometry functions vectorization via SLEEF: http://sleef.org/.

- A new vectorization library enum is added to TargetLibraryInfo.h: SLEEF.
- A new option is added to TargetLibraryInfoImpl - ClVectorLibrary: SLEEF.
- A comprehensive test case is included in this changeset.
- A new vectorization library argument is added to -fveclib: -fveclib=SLEEF.

Trigonometry functions that are vectorized by sleef:
acos
asin
atan
atanh
cos
cosh
exp
exp2
exp10
lgamma
log10
log2
log
sin
sinh
sqrt
tan
tanh
tgamma

Co-authored-by: Stefan Teleman

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D134719

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Add parameter extension attributes in various instrumentation passes.

For the targets that have in their ABI the requirement that arguments and
return values are extended to the full register bitwid

Add parameter extension attributes in various instrumentation passes.

For the targets that have in their ABI the requirement that arguments and
return values are extended to the full register bitwidth, it is important
that calls when built also take care of this detail.

The OMPIRBuilder, AddressSanitizer, GCOVProfiling, MemorySanitizer and
ThreadSanitizer passes are with this patch hopefully now doing this properly.

Reviewed By: Eli Friedman, Ulrich Weigand, Johannes Doerfert

Differential Revision: https://reviews.llvm.org/D133949

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