Use VPTERNLOG for 3-operands boolean functions.

Signed-off-by: Nicola Torracca <nicola.torracca@gmail.com>

Use embedded broadcast to replicate constants for AVX512.

Signed-off-by: Nicola Torracca <shark@bitchx.it>

Bump minimum NASM version

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

sm3: add v2.24 API compatibility compilation mode and
move some defines from public to internal header file

Signed-off-by: Tomasz Kantecki <tomasz.kantecki@intel.com>

sm3: deprecate old SM3 multi-buffer API

Signed-off-by: Tomasz Kantecki <tomasz.kantecki@intel.com>

multibuffer: add ISAL_ prefix to hash multibuffer enums

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

sm3_mb: return invalid algorithm if FIPS mode is enabled at start of the function

Also return the error in the init function.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

sm3_mb: return invalid algorithm if FIPS_MODE is enabled

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

sm3_mb: add param check test

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

sm3_mb: add new api with parameter checking

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

fix compiler messages on windows

Fix warnings generated by MSVC with /W3

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

test: fixes for test applications compilation issues on windows

Signed-off-by: Tomasz Kantecki <tomasz.kantecki@intel.com>

sm3_mb: reformat with new coding style

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

sm3_mb: fix memory leaks in test apps

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

lib: clear mb mgrs when initializing

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

Fix a handful of spelling mistakes and typos

Fixed outstanding spelling mistakes and typos in comments and
variables found using codespell

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.c

Fix a handful of spelling mistakes and typos

Fixed outstanding spelling mistakes and typos in comments and
variables found using codespell

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

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Fix the problem that sve functions cannot be debugged by gdb

Signed-off-by: chenxuqiang <cxq507@foxmail.com>

sm3_mb optimization by SVE2 for aarch64

Test result on N2/V1 micro-architecture:

+--------+-------------+-------------+------------+
| | CPU1 (N2) | CPU2 (N2) | CPU3 (V1) |
| | 1

sm3_mb optimization by SVE2 for aarch64

Test result on N2/V1 micro-architecture:

+--------+-------------+-------------+------------+
| | CPU1 (N2) | CPU2 (N2) | CPU3 (V1) |
| | 128-bit VL | 128-bit VL | 256-bit VL |
+--------+-------------+-------------+------------+
| neon | 397 MB/s | 495 MB/s | 464 MB/s |
+--------+-------------+-------------+------------+
| sve2 | 425 MB/s | 516 MB/s | |
| | (+7%) | (+4.2%) |
+--------+-------------+-------------+------------+
| sve | | | 652 MB/s |
| | | | (+40%) |
+--------+-------------+-------------+------------+

Change-Id: Ie73098d45a83eb438cdf3121d97d10e477ea9665
Signed-off-by: Daniel Hu <Daniel.Hu@arm.com>

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test: Change perf tests to warm by default

The cold versions of tests depended on a fixed size of last level
cache that is too low on some arch and too high for the total
available memory on others.

test: Change perf tests to warm by default

The cold versions of tests depended on a fixed size of last level
cache that is too low on some arch and too high for the total
available memory on others.

Change-Id: I4bfbb46b6f686aa1542337abd68f0b34c40c450b
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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Add twice non-blocksize align test

If non-blocksize data is submited twice, the first commit will
be abondaned. This commit is to fix that

Change-Id: Ida8f08ff226ab894d84ff62f5806b5989d6d9e3a
Signe

Add twice non-blocksize align test

If non-blocksize data is submited twice, the first commit will
be abondaned. This commit is to fix that

Change-Id: Ida8f08ff226ab894d84ff62f5806b5989d6d9e3a
Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

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fix base function fail

If input data size less than Block size twice, the result will
be wrong for base functions

Change-Id: Iba47853a184d7765fe466c0e5e216134e9cdd009
Signed-off-by: Jerry Yu <jerry

fix base function fail

If input data size less than Block size twice, the result will
be wrong for base functions

Change-Id: Iba47853a184d7765fe466c0e5e216134e9cdd009
Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

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SM3 mb optimization for aarch64 by SVE

This patch optimize the sm3-mb algorithm using the SVE feature
of aarch64. SVE is optional feature for ARM v8

Tested on modern micro-architecture, it shows an

SM3 mb optimization for aarch64 by SVE

This patch optimize the sm3-mb algorithm using the SVE feature
of aarch64. SVE is optional feature for ARM v8

Tested on modern micro-architecture, it shows an 39% uplift in
performance over neon

Change-Id: Icb674de67284d44a8d73f0b5d9e12ff637e8fdac
Signed-off-by: Daniel Hu <Daniel.Hu@arm.com>

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mb_hash: Add pragmas in mb scheduler to limit vex transitions

Change-Id: Ida7474eb298491cbd8e64505e162e4d096a373d2
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

Fix lane handling on aarch64 systems with SM3 hardware crypto support

This fixes .unused_lanes to be initialised to (e.g.) 0xF3210 instead of
the current 0xF0123.

Without this, sm3_mb_rand_update_t

Fix lane handling on aarch64 systems with SM3 hardware crypto support

This fixes .unused_lanes to be initialised to (e.g.) 0xF3210 instead of
the current 0xF0123.

Without this, sm3_mb_rand_update_test and sm3_mb_vs_ossl_perf spin in
infinite loops calling sm3_ctx_mgr_submit().

Change-Id: I878228481408d4d5c34724ff1170e10670a4c48c
Signed-off-by: Tom Cosgrove <tom.cosgrove@arm.com>

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Always check the result of posix_memalign() calls

Also, use same return value when these fail (+1) as used when the output pointer
is NULL, rather than using -1. This avoids potential issues when re

Always check the result of posix_memalign() calls

Also, use same return value when these fail (+1) as used when the output pointer
is NULL, rather than using -1. This avoids potential issues when results are
combined with with `errors += foo()`.

Change-Id: I0cfa73481315366cd3b8bd7f369fae55960a88a4
Signed-off-by: Tom Cosgrove <tom.cosgrove@arm.com>

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