Use embedded broadcast to replicate constants for AVX512.

Signed-off-by: Nicola Torracca <shark@bitchx.it>

Bump minimum NASM version

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

mh_sha1: add isal prefix to context struct

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

mh_sha1: remove unused avx512 symbol

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

mh_sha1: add ISAL_ prefix to MH SHA1 definitions

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

mh_sha1: deprecate old API

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

mh_sha1: rename internal API

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

mh_sha1: return invalid algorithm if FIPS mode is enabled at start of the function

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

mh_sha1: replace prefetchnta to prefetcht1

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

mh_sha1: return invalid algorithm if FIPS_MODE is enabled

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

fix compiler messages on windows

Fix warnings generated by MSVC with /W3

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

mh_sha1: reformat with new coding style

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

update expected arg passed to CHECK_RETURN_LABEL macro

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

rename CHECK_RETURN macro and move to test.h

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

mh_sha1: add new api with parameter checking

Add new MH SHA1 input validation test app

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

mh_sha1: check returned value and free resources in perf app

Also returned value is not checked while benchmarking the functions
on purpose.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel

mh_sha1: check returned value and free resources in perf app

Also returned value is not checked while benchmarking the functions
on purpose.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

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mh_sha1: remove deadcode

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

mh_sha1: fix memory leaks in test apps

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

Fix a handful of spelling mistakes and typos

Fixed outstanding spelling mistakes and typos in comments and
variables found using codespell

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.c

Fix a handful of spelling mistakes and typos

Fixed outstanding spelling mistakes and typos in comments and
variables found using codespell

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

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Fix the problem that sve functions cannot be debugged by gdb

Signed-off-by: chenxuqiang <cxq507@foxmail.com>

Optimize the sha1-mh on aarch64 by SVE/SVE2

Here are the test results on N2/V1 micro-architecture:

---------+-------------+-------------+------------+
| | CPU0 (N2) | CPU2 (N2) | CPU3 (

Optimize the sha1-mh on aarch64 by SVE/SVE2

Here are the test results on N2/V1 micro-architecture:

---------+-------------+-------------+------------+
| | CPU0 (N2) | CPU2 (N2) | CPU3 (V1) |
| | 128-bit VL | 128-bit VL | 256-bit VL |
+--------+-------------+-------------+------------+
| neon | 923 MB/s | 1002 MB/s | 930 MB/s |
+--------+-------------+-------------+------------+
| sve2 | 1146 MB/s | 1634 MB/s | |
| | (+24%) | (+63%) | |
+--------+-------------+-------------+------------+
| sve | | | 1465 MB/s |
| | | | (+57.5) |
+--------+-------------+-------------+------------+

Change-Id: Id19f73ec75bd283cca628c0ff516289adb0ac4ff
Signed-off-by: Daniel Hu <Daniel.Hu@arm.com>

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test: Change perf tests to warm by default

The cold versions of tests depended on a fixed size of last level
cache that is too low on some arch and too high for the total
available memory on others.

test: Change perf tests to warm by default

The cold versions of tests depended on a fixed size of last level
cache that is too low on some arch and too high for the total
available memory on others.

Change-Id: I4bfbb46b6f686aa1542337abd68f0b34c40c450b
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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Enhance mh_sha1 for aarch64 over ASIMD

This patch improves the mh_sha1 ASIMD implementation for aarch64,
with following changes:
* Load 4-lane one block of data into ASIMD registers, to save the tim

Enhance mh_sha1 for aarch64 over ASIMD

This patch improves the mh_sha1 ASIMD implementation for aarch64,
with following changes:
* Load 4-lane one block of data into ASIMD registers, to save the time
to load memory inside each SHA1 step
* Remove one vector MOV instruction per SHA1 step
* Streamlined code to enable sharing the code between algs

Change-Id: If13741032b62b23e8a9f89418847154f9deea26e
Signed-off-by: Daniel Hu <Daniel.Hu@arm.com>

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test: Fix hash reference functions for gcc11 issue

Starting with gcc11, optimization is causing the hash reference
functions to fail on O2 but not on O1. Likely a gcc middle-end
bug (https://gcc.gnu

test: Fix hash reference functions for gcc11 issue

Starting with gcc11, optimization is causing the hash reference
functions to fail on O2 but not on O1. Likely a gcc middle-end
bug (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101257) that
causes violation of strict-aliasing rules. Until a work around
is found, this uses an attribute to roll back ipa.

Change-Id: Ie525bb890f59b6a1ab83f42e3951a4b85f45bd8c
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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Accelerate mh-sha1 by ASIMD on aarch64

This patch use the Advanced SIMD of aarch64 to accelerate mh_sha1

Change-Id: I321c68a8175e1ac8a3ffa74c9fb916f8bba4832d
Signed-off-by: Daniel Hu <Daniel.Hu@arm

Accelerate mh-sha1 by ASIMD on aarch64

This patch use the Advanced SIMD of aarch64 to accelerate mh_sha1

Change-Id: I321c68a8175e1ac8a3ffa74c9fb916f8bba4832d
Signed-off-by: Daniel Hu <Daniel.Hu@arm.com>

show more ...