History log of /isa-l_crypto/Makefile.am (Results 1 – 25 of 35)
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Revision tags: v2.25.0
# 3aa2266b 23-May-2024 Pablo de Lara <pablo.de.lara.guarch@intel.com>

build: Bump revision to 2.25

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>


# 151e9bca 14-May-2024 Pablo de Lara <pablo.de.lara.guarch@intel.com>

Remove YASM support

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>


# fea2d86a 22-May-2024 Marcel Cornu <marcel.d.cornu@intel.com>

add API to get library version and version test app

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>


# fa6261a4 04-Apr-2024 Pablo de Lara <pablo.de.lara.guarch@intel.com>

build: remove unneeded flags

These compilation flags are passed/defined in configure.ac

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>


# 5e4dc74c 02-Apr-2024 Pablo de Lara <pablo.de.lara.guarch@intel.com>

lib: add self tests API

Add common isal_self_tests() function that runs all the self tests
available.

This function is called at the start of every single NIST-approved
crypto function.

Signed-off

lib: add self tests API

Add common isal_self_tests() function that runs all the self tests
available.

This function is called at the start of every single NIST-approved
crypto function.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

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# 7b5b2f46 20-Mar-2024 Marcel Cornu <marcel.d.cornu@intel.com>

add build option to disable parameter checking

Enabled by default

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>


# 59de7709 26-Feb-2024 Pablo de Lara <pablo.de.lara.guarch@intel.com>

Makefile: add SAFE_DATA parameter to clear sensitive data

This parameter will be enabled by default, which might impact
performance, but it will enhance the security of the crypto
implementations in

Makefile: add SAFE_DATA parameter to clear sensitive data

This parameter will be enabled by default, which might impact
performance, but it will enhance the security of the crypto
implementations in certain conditions.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

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# f2e0339b 23-Oct-2023 chenxuqiang <cxq507@foxmail.com>

fix redefined warning on aarch64 when using autoconf 2.71

Signed-off-by: chenxuqiang <cxq507@foxmail.com>


# 2118044b 25-Mar-2022 Daniel Hu <Daniel.Hu@arm.com>

Fix the build issue for CPU other than x86/aarch64

AES acceleration is not implemented for other CPU, like ppc64, etc
AES related function can't compile on these platforms

Change-Id: I082b2b9323deb

Fix the build issue for CPU other than x86/aarch64

AES acceleration is not implemented for other CPU, like ppc64, etc
AES related function can't compile on these platforms

Change-Id: I082b2b9323debc7f5691dd3494991bbfec0e54e8
Signed-off-by: Daniel Hu <Daniel.Hu@arm.com>

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# 99d3b449 20-Jan-2022 H.J. Lu <hjl.tools@gmail.com>

Properly add .note.gnu.property section to assembly codes

1. Partially revert

commit 7f8ce0f8177a2d76dfa7fc57f3f9af08eaf259e2
Author: John Kariuki <John.K.Kariuki@intel.com>
Date: Wed Jun 3 12:22

Properly add .note.gnu.property section to assembly codes

1. Partially revert

commit 7f8ce0f8177a2d76dfa7fc57f3f9af08eaf259e2
Author: John Kariuki <John.K.Kariuki@intel.com>
Date: Wed Jun 3 12:22:52 2020 -0700

x86: add support for Intel CET

which includes a hack to work around the old nasm which doesn't support

section .note.gnu.property note alloc noexec align=8

This hack doesn't work for downstream which doesn't use the hack.

2. If Intel CET is enabled, require nasm with note section support to
add

section .note.gnu.property note alloc noexec align=N

to assembly codes.

Verified with

$ CC="gcc -Wl,-z,cet-report=error -fcf-protection" CXX="g++ -Wl,-z,cet-report=error -fcf-protection" .../configure x86_64-linux
$ make -j8

on Tiger Lake.

Change-Id: I2f7930798aab9fe084919432b59799bb34884b3e
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>

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# 54b8d5ce 11-Jun-2021 Daniel Hu <Daniel.Hu@arm.com>

XTS AES implementation for aarch64

This patch implements XTS AES 128/256 using the cpu feature ASIMD and Crypto Extension

Change-Id: I8fcb80a5b698bd42097c1ec76168f925c287389f
Signed-off-by: Daniel

XTS AES implementation for aarch64

This patch implements XTS AES 128/256 using the cpu feature ASIMD and Crypto Extension

Change-Id: I8fcb80a5b698bd42097c1ec76168f925c287389f
Signed-off-by: Daniel Hu <Daniel.Hu@arm.com>

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Revision tags: v2.24.0
# df9091af 16-Apr-2021 Greg Tucker <greg.b.tucker@intel.com>

build: Bump revision to 2.24

Change-Id: Idd781828bab120bcdc346bde1dc466a9f2619575
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>


# d7dccff4 30-Oct-2020 Jerry Yu <jerry.h.yu@arm.com>

aes: Implement aes-gcm128/256 with crypto extension

Change-Id: Ib460f9d3f45a18db095f4b496ae11f1cb31ba185
Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>


# 92aa5aa4 28-Oct-2020 Greg Tucker <greg.b.tucker@intel.com>

Fix endian helper for distcheck and internal only

Previously included file endian_helper.h was not included in the
distribution list and was included by external headers. This changes
the includes t

Fix endian helper for distcheck and internal only

Previously included file endian_helper.h was not included in the
distribution list and was included by external headers. This changes
the includes to be local only and puts file in non-external dist list.
Also fixes other missing extra-dist.

Fixes #59

Change-Id: I643da8c26b6136a9f1bba5493936dd1184c217d5
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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Revision tags: v2.23.0
# 17570868 25-Sep-2020 Greg Tucker <greg.b.tucker@intel.com>

Include doxygen label in toplevel header

Change-Id: Ifbb8b93d502291f96d470bb44c5004bae97d3303
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>


# 62ab114c 24-Sep-2020 Greg Tucker <greg.b.tucker@intel.com>

build: Bump revision to 2.23

Change-Id: Ifb25c6073c505d12e82e9fc3112f94bb80158ca2
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>


# 7f8ce0f8 03-Jun-2020 John Kariuki <John.K.Kariuki@intel.com>

x86: add support for Intel CET

This patch generates .note.gnu.property section for ELF output
and adds endbranch to all indirect branch targets.

Signed-off-by: John Kariuki <John.K.Kariuki@intel.co

x86: add support for Intel CET

This patch generates .note.gnu.property section for ELF output
and adds endbranch to all indirect branch targets.

Signed-off-by: John Kariuki <John.K.Kariuki@intel.com>
Change-Id: I622a546bf9b9590e11d4b4eda3d6828ea0a4e53f

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# c22a0636 24-Oct-2019 Jerry Yu <jerry.h.yu@arm.com>

build: fix cross compile break

For cross compile , assembly compile report fail.
It is due to the wrong compiler setting.

Change-Id: Ia1b664ceca833c8c73f403f2e187b42c19a44b06
Signed-off-by: Jerry Y

build: fix cross compile break

For cross compile , assembly compile report fail.
It is due to the wrong compiler setting.

Change-Id: Ia1b664ceca833c8c73f403f2e187b42c19a44b06
Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

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Revision tags: v2.22.0
# dc44e3c3 25-Jul-2019 Jerry Yu <jerry.h.yu@arm.com>

build: add base aliases files

- Revert sha1_mb to base aliases functions for multi-arch
- Disable aes support due to no base aliases available

Change-Id: I89fd0a76b98fb5014818637944fb73608e4c4246
S

build: add base aliases files

- Revert sha1_mb to base aliases functions for multi-arch
- Disable aes support due to no base aliases available

Change-Id: I89fd0a76b98fb5014818637944fb73608e4c4246
Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

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# 78729256 17-Aug-2019 Greg Tucker <greg.b.tucker@intel.com>

build: Bump revision to 2.22

Change-Id: I2aa7413930600ae33b9d6df9f7c2b3c951c94977
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>


# 449703d9 12-Apr-2019 Chunyang Hui <chunyang.hui@intel.com>

sm3_mb: Add base function support for sm3

Change-Id: Ica4f6d7be4453daa73df2a4d15e9dca7cc0f603a
Signed-off-by: Chunyang Hui <chunyang.hui@intel.com>


# ffd20d8c 13-Feb-2019 Jerry Yu <jerry.h.yu@arm.com>

build: Add multi-arch support

The patch is to add multi-arch support and it is verified
on aarch64 platform .
- build pass for arm64(host is aarch64)
- remove multibinary support for aarch64
- add m

build: Add multi-arch support

The patch is to add multi-arch support and it is verified
on aarch64 platform .
- build pass for arm64(host is aarch64)
- remove multibinary support for aarch64
- add multi arch support
- verified below make commands
- ./autogen.sh && ./configure && make && make check \
&& make perf
- make -f Makefile.unx check perf

Change-Id: Ic3cd3d2b554e2ea472896ced2c01c95e16fb6efc
Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

show more ...


# c995a885 03-May-2019 Greg Tucker <greg.b.tucker@intel.com>

build: Install pkg-config files

Change-Id: Ied96c40d39541fa7c1cb52480a406f042ca7e1a1
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>


Revision tags: v2.21.0
# b45447b7 20-Dec-2017 Greg Tucker <greg.b.tucker@intel.com>

build: Bump revision to 2.21

Change-Id: I4676913fde00c42950e3b1c7f6c9f85d2ea54d3b
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>


Revision tags: v2.20.0
# 7fd405e9 28-Sep-2017 Greg Tucker <greg.b.tucker@intel.com>

doc: Add doxyfile and build for auto API doc gen

Change-Id: Id46b1b575725098538dc7552a0440ac8f8271b2c
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>


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