crc: reformat using new code style

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

Fix mach compilation again; fold_constant has to be the same section as crc16_t10dif_copy_pmull

Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>

Fix a handful of spelling mistakes and typos

There are quite a few spelling mistakes and typos in comments and
user facing message literal strings as found using codespell. Fix
these.

Signed-off-by

Fix a handful of spelling mistakes and typos

There are quite a few spelling mistakes and typos in comments and
user facing message literal strings as found using codespell. Fix
these.

Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

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crc: use macro to print 64-bit value

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

crc: [test] fix memory leak

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

crc: fix build warnings on Windows

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

lib: reduce verbosity by default in tests

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

crc: fix build with NASM 2.14

Fix following compilation error
crc/crc32_iscsi_by16_10.s:408: error: invalid combination of opcode and operands

Fixes #257.

Signed-off-by: Pablo de Lara <pablo.de.la

crc: fix build with NASM 2.14

Fix following compilation error
crc/crc32_iscsi_by16_10.s:408: error: invalid combination of opcode and operands

Fixes #257.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

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crc: optimize by supporting arm xor fusion feature

Arrange the two xor instructions according to the specified
paradigm, then the two xor instructions can be fused to execute
which can save one issu

crc: optimize by supporting arm xor fusion feature

Arrange the two xor instructions according to the specified
paradigm, then the two xor instructions can be fused to execute
which can save one issue slot and one execution latency.

Change-Id: Ic64bcfe569b2468e4dc9c13d073d367cc81fd937
Signed-off-by: liuqinfei <lucas.liuqinfei@huawei.com>

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crc: fold 64 bytes of data if possible

When less than 256 bytes of data are left, fold data
in steps of 64 bytes, instead of 16 bytes, if there is enough
data.

Change-Id: I47d7cacdd1ba620078df52813

crc: fold 64 bytes of data if possible

When less than 256 bytes of data are left, fold data
in steps of 64 bytes, instead of 16 bytes, if there is enough
data.

Change-Id: I47d7cacdd1ba620078df528136945695c338db6d
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

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crc: optimize last bytes

Change-Id: I4b8f73b23eb50c4c50ca65fab19716f217fe5780
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

crc: add CRC64 rocksoft implementation

- Added reference implementation
- Added base implementation
- Added functional and performance tests

Change-Id: I60c5097bd5fb89ee7a50910e71d449d50d155d0a
Sig

crc: add CRC64 rocksoft implementation

- Added reference implementation
- Added base implementation
- Added functional and performance tests

Change-Id: I60c5097bd5fb89ee7a50910e71d449d50d155d0a
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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crc: refactor SSE CRC64 implementations to use common code

Change-Id: I2d141f2ccd12ab338783e50736e36ed4aeb11f7f
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

crc: use k-mask to load final bytes of data

Change-Id: Ibd8d2144bc6942e11911e25a6365c1cb108af477
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

crc: Use ternlog in by16 avx512 loop

Ternlog has additional benefit in by16 crc main loop in both reflected
and non-reflected polynomial crcs. Some arch see 4-7% improvement.
Revisited on suggestion

crc: Use ternlog in by16 avx512 loop

Ternlog has additional benefit in by16 crc main loop in both reflected
and non-reflected polynomial crcs. Some arch see 4-7% improvement.
Revisited on suggestion by Nicola Torracca.

Change-Id: I806266a7080168cf33409634983e254a291a0795
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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Fixes for aarch64 mac

- It should be fine to enable pmull always on Apple Silicon
- macOS 12+ is required for PMULL instruction.
- Changed the conditional macro to __APPLE__
- Rewritten dispatcher u

Fixes for aarch64 mac

- It should be fine to enable pmull always on Apple Silicon
- macOS 12+ is required for PMULL instruction.
- Changed the conditional macro to __APPLE__
- Rewritten dispatcher using sysctlbyname
- Use __USER_LABEL_PREFIX__
- Use __TEXT,__const as readonly section
- use ASM_DEF_RODATA macro
- fix func decl

Change-Id: I800593f21085d8187b480c8bb3ab2bd70c4a6974
Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>

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test: Change perf tests to warm by default

The cold versions of tests depended on a fixed size of last level
cache that is too low on some arch and too high for the total
available memory on others.

test: Change perf tests to warm by default

The cold versions of tests depended on a fixed size of last level
cache that is too low on some arch and too high for the total
available memory on others.

Change-Id: Iee98403f9ace02e01b810c296a5fe44b933bfb17
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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Remove all slver legacy segments

The relic slver is no longer used for individual versioning
on functions and is confusing tools looking for data in text
sections. This removes all instances instead

Remove all slver legacy segments

The relic slver is no longer used for individual versioning
on functions and is confusing tools looking for data in text
sections. This removes all instances instead of fixing since
its usefulness is waining. Fixes #221

Change-Id: Ife0b9f105950a90337c58e8a41ac2cffc0f67d99
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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crc16: Accelerate T10DIF performance with prefetch and pmull2

The memory block size calculated by t10dif is generally 512 bytes in
sectors. prefetching can effectively reduce cache misses.Use ldp in

crc16: Accelerate T10DIF performance with prefetch and pmull2

The memory block size calculated by t10dif is generally 512 bytes in
sectors. prefetching can effectively reduce cache misses.Use ldp instead
of ldr to reduce the number of instructions, pmull+pmull2 can resuce
register access. The perf test result shows that the performance is
improved by 5x ~ 14x after optimization.

Change-Id: Ibd3f08036b6a45443ffc15f808fd3b467294c283
Signed-off-by: Chunsong Feng <fengchunsong@huawei.com>

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build: Remove unneeded file types.h

The file types.h has long been misnamed and overlaps with
functionality in the test helper routines.

Change-Id: I774047d3a0074198b67a6b4e909f1e2ce1938195
Signed-

build: Remove unneeded file types.h

The file types.h has long been misnamed and overlaps with
functionality in the test helper routines.

Change-Id: I774047d3a0074198b67a6b4e909f1e2ce1938195
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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perf: Remove unneeded time include

Timing functions are made os-independent with test.h include.

Change-Id: Iab7d6325254d5c32263504efc756dbbe51d77153
Signed-off-by: Greg Tucker <greg.b.tucker@intel

perf: Remove unneeded time include

Timing functions are made os-independent with test.h include.

Change-Id: Iab7d6325254d5c32263504efc756dbbe51d77153
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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crc: Fix warning in perf test from uninitialized tmp ptr

Both gcc and clang are showing a warning on this despite the buffer
always being set before use.

Change-Id: I0e8f6b9e3451efe69e49814abc883d4

crc: Fix warning in perf test from uninitialized tmp ptr

Both gcc and clang are showing a warning on this despite the buffer
always being set before use.

Change-Id: I0e8f6b9e3451efe69e49814abc883d49b04f2666
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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crc: Add new vclmul version of crc32_iscsi

Change-Id: I1c509c6ea312b6eb4e1c2c1c8bb7044f7b043e0d
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

crc32: tweak performance of crc32/crc32c

Tweak performances with prefetch instructions.

Below is the test results:
- Neoverse N1: ~30%
- Cortex-A72: ~3%
- Cortex-A57: ~90%
- Others: 50% - 5x

Chang

crc32: tweak performance of crc32/crc32c

Tweak performances with prefetch instructions.

Below is the test results:
- Neoverse N1: ~30%
- Cortex-A72: ~3%
- Cortex-A57: ~90%
- Others: 50% - 5x

Change-Id: I3ab292a953043dbaea98af3c66778f57da3a1331
Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

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x86: Add ENDBR32/ENDBR64 at function entries for Intel CET

To support Intel CET, all indirect branch targets must start with
ENDBR32/ENDBR64. Here is a patch to define endbranch and add it to
funct

x86: Add ENDBR32/ENDBR64 at function entries for Intel CET

To support Intel CET, all indirect branch targets must start with
ENDBR32/ENDBR64. Here is a patch to define endbranch and add it to
function entries in x86 assembly codes which are indirect branch
targets as discovered by running testsuite on Intel CET machine and
visual inspection.

Verified with

$ CC="gcc -Wl,-z,cet-report=error -fcf-protection" CXX="g++ -Wl,-z,cet-report=error -fcf-protection" .../configure x86_64-linux
$ make -j8
$ make -j8 check

with both nasm and yasm on both CET and non-CET machines.

Change-Id: I9822578e7294fb5043a64ab7de5c41de81a7d337
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>

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