| 353e3639 | 27-Sep-2024 |
Nicolas Chautru <nicolas.chautru@intel.com> |
bbdev: add queue debug dump
This provides a new API to dump more debug information
related to the status on a given bbdev queue.
Some of this information is visible at bbdev level.
This also provide
bbdev: add queue debug dump
This provides a new API to dump more debug information
related to the status on a given bbdev queue.
Some of this information is visible at bbdev level.
This also provides a new option dev op, to print more
information at the lower PMD level.
This helps user to troubleshoot issues related to
previous operations provided into a queue causing
possible hard-to-debug negative scenarios.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
show more ...
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| e797d009 | 15-Jun-2023 |
Nicolas Chautru <nicolas.chautru@intel.com> |
bbdev: improve error handling for queue configuration
Refactor of the error handling based on available priority
queue to be more generic.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
bbdev: improve error handling for queue configuration
Refactor of the error handling based on available priority
queue to be more generic.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
show more ...
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| f4e6c4ef | 15-Jun-2023 |
Nicolas Chautru <nicolas.chautru@intel.com> |
bbdev: add new capability for FEC 5G UL processing
Extending existing LDPC UL operation for new capability.
Option to compress HARQ memory to 4 bits per LLR.
Signed-off-by: Nicolas Chautru <nicolas
bbdev: add new capability for FEC 5G UL processing
Extending existing LDPC UL operation for new capability.
Option to compress HARQ memory to 4 bits per LLR.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
show more ...
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| 0aa8b208 | 15-Jun-2023 |
Nicolas Chautru <nicolas.chautru@intel.com> |
bbdev: add new capabilities for FFT processing
Extending existing FFT operation for new capabilities.
Optional frequency domain dewindowing, frequency resampling,
timing error correction and time of
bbdev: add new capabilities for FFT processing
Extending existing FFT operation for new capabilities.
Optional frequency domain dewindowing, frequency resampling,
timing error correction and time offset per CS.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Maxime Coquelin <maxime.coquelin@redhat.com>
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| ed090599 | 20-Mar-2023 |
Tyler Retzlaff <roretzla@linux.microsoft.com> |
rework atomic intrinsics fetch operations
Use __atomic_fetch_{add,and,or,sub,xor} instead of
__atomic_{add,and,or,sub,xor}_fetch adding the necessary code to
allow consumption of the resulting value
rework atomic intrinsics fetch operations
Use __atomic_fetch_{add,and,or,sub,xor} instead of
__atomic_{add,and,or,sub,xor}_fetch adding the necessary code to
allow consumption of the resulting value.
Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
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| b3af2227 | 04-Oct-2022 |
Nicolas Chautru <nicolas.chautru@intel.com> |
bbdev: remove unnecessary checks
Code clean up due to if-check not required
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Acked-b
bbdev: remove unnecessary checks
Code clean up due to if-check not required
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
show more ...
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