pipeline: rework optimization pattern for header generation

The P4 language requires marking a header as valid before any of the
header fields are written as opposed to after the writes are done.
He

pipeline: rework optimization pattern for header generation

The P4 language requires marking a header as valid before any of the
header fields are written as opposed to after the writes are done.
Hence, the optimization of replacing the sequence of instructions to
generate a header by reading it from the table action data with a
single DMA internal instruction are reworked from "mov all + validate
-> dma" to "validate + mov all -> dma".

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>

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pipeline: auto-detect endianness of action arguments

Each table entry is made up of match fields and action data, with the
latter made up of the action ID and the action arguments. The approach
of h

pipeline: auto-detect endianness of action arguments

Each table entry is made up of match fields and action data, with the
latter made up of the action ID and the action arguments. The approach
of having the user specify explicitly the endianness of the action
arguments is difficult to be picked up by P4 compilers, as the P4
compiler is generally unaware about this aspect.

This commit introduces the auto-detection of the endianness of the
action arguments by examining the endianness of the their destination:
network byte order (NBO) when they get copied to headers and host byte
order (HBO) when they get copied to packet meta-data or mailboxes.

The endianness specification of each action argument as part of the
rule specification, e.g. H(...) and N(...) is removed from the rule
file and auto-detected based on their destination. The DMA instruction
scope is made internal, so mov instructions need to be used. The
pattern of transferring complete headers from table entry action args
to headers is detected, and the associated set of mov instructions
plus header validate is internally detected and replaced with the
internal-only DMA instruction to preserve performance.

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>

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pipeline: add drop instruction to SWX

Enabled the TX instruction to accept an immediate value for the output
port argument. The drop instruction is simply an alias to the TX
instruction for the last

pipeline: add drop instruction to SWX

Enabled the TX instruction to accept an immediate value for the output
port argument. The drop instruction is simply an alias to the TX
instruction for the last output port of the pipeline.

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>

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examples/pipeline: add VXLAN encapsulation example

Add VXLAN encapsulation example to the SWX pipeline application. The
VXLAN tunnels can be generated with the vxlan_table.py script. Example
command

examples/pipeline: add VXLAN encapsulation example

Add VXLAN encapsulation example to the SWX pipeline application. The
VXLAN tunnels can be generated with the vxlan_table.py script. Example
command line: ./build/pipeline -l0-1 -- -s ./examples/vxlan.cli

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>

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