power: rename files for CPU frequency management

This patch renames the existing core power library source files
from rte_power.* to rte_power_cpufreq.* for better clarity

Signed-off-by: Sivaprasad

power: rename files for CPU frequency management

This patch renames the existing core power library source files
from rte_power.* to rte_power_cpufreq.* for better clarity

Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com>

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examples: fix port ID restriction

Currently application supports port IDs up to 255
irrespective of RTE_MAX_ETHPORTS.

The patch fixes these constraints by allowing port
IDs up to RTE_MAX_ETHPORTS.

examples: fix port ID restriction

Currently application supports port IDs up to 255
irrespective of RTE_MAX_ETHPORTS.

The patch fixes these constraints by allowing port
IDs up to RTE_MAX_ETHPORTS.

Fixes: af75078fece3 ("first public release")
Fixes: f88e7c175a68 ("examples/l3fwd-power: add high/regular perf cores options")
Fixes: 08bd1a174461 ("examples/l3fwd-graph: add graph-based l3fwd skeleton")
Fixes: d299106e8e31 ("examples/ipsec-secgw: add IPsec sample application")
Cc: stable@dpdk.org

Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@huawei.com>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
Acked-by: Ferruh Yigit <ferruh.yigit@amd.com>

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examples: fix lcore ID restriction

Currently the config option allows lcore IDs up to 255,
irrespective of RTE_MAX_LCORES and needs to be fixed.

The patch fixes these constraints by allowing all
lc

examples: fix lcore ID restriction

Currently the config option allows lcore IDs up to 255,
irrespective of RTE_MAX_LCORES and needs to be fixed.

The patch fixes these constraints by allowing all
lcore IDs up to RTE_MAX_LCORES.

Fixes: af75078fece3 ("first public release")
Fixes: f88e7c175a68 ("examples/l3fwd-power: add high/regular perf cores options")
Fixes: 08bd1a174461 ("examples/l3fwd-graph: add graph-based l3fwd skeleton")
Fixes: d299106e8e31 ("examples/ipsec-secgw: add IPsec sample application")
Fixes: 0e8f47491f09 ("examples/vm_power: add command to query CPU frequency")
Fixes: de3cfa2c9823 ("sched: initial import")
Cc: stable@dpdk.org

Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@huawei.com>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
Acked-by: Ferruh Yigit <ferruh.yigit@amd.com>

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examples: fix queue ID restriction

Currently application supports Rx queue IDs up to 255
and max queues of 256 irrespective of device support.
This limits the number of active lcores to 256.

The pa

examples: fix queue ID restriction

Currently application supports Rx queue IDs up to 255
and max queues of 256 irrespective of device support.
This limits the number of active lcores to 256.

The patch fixes these constraints by increasing
the Rx queue IDs to support up to 65535.

Fixes: af75078fece3 ("first public release")
Fixes: f88e7c175a68 ("examples/l3fwd-power: add high/regular perf cores options")
Fixes: 08bd1a174461 ("examples/l3fwd-graph: add graph-based l3fwd skeleton")
Cc: stable@dpdk.org

Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@huawei.com>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
Acked-by: Ferruh Yigit <ferruh.yigit@amd.com>

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examples: move alignment attribute on types for MSVC

Move location of __rte_aligned(a) to new conventional location. The new
placement between {struct,union} and the tag allows the desired
alignment

examples: move alignment attribute on types for MSVC

Move location of __rte_aligned(a) to new conventional location. The new
placement between {struct,union} and the tag allows the desired
alignment to be imparted on the type regardless of the toolchain being
used for both C and C++. Additionally, it avoids confusion by Doxygen
when generating documentation.

Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
Reviewed-by: Morten Brørup <mb@smartsharesystems.com>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>

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eal: remove unneeded includes from a public header

Do not include <ctype.h>, <errno.h>, and <stdlib.h> from <rte_common.h>,
because they are not used by this file.
Include the needed headers directl

eal: remove unneeded includes from a public header

Do not include <ctype.h>, <errno.h>, and <stdlib.h> from <rte_common.h>,
because they are not used by this file.
Include the needed headers directly from the files that need them.

Signed-off-by: Dmitry Kozlyuk <dmitry.kozliuk@gmail.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>

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examples/l3fwd-power: fix updating lcore parameters

When perf-config option is specified, we are calling into the power
library even though it may not necessarily be enabled. It is
questionable whet

examples/l3fwd-power: fix updating lcore parameters

When perf-config option is specified, we are calling into the power
library even though it may not necessarily be enabled. It is
questionable whether perf-config option is even applicable to non-power
library modes, but for now, fix it just by avoiding calling into the
power library if it wasn't initialized, and assume that every lcore is
high performance core.

Fixes: e0194feb322c ("examples/l3fwd-power: add interrupt-only mode")

Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
Acked-by: David Hunt <david.hunt@intel.com>

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remove extra blank lines at end of files

There should not be blank lines at end of files.

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Bruce Richardson <bruce.richardson@

remove extra blank lines at end of files

There should not be blank lines at end of files.

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>

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examples/l3fwd-power: add high/regular perf cores options

Added high/regular performance core pinning configuration options
that can be used in place of the existing 'config' option.

'--high-perf-c

examples/l3fwd-power: add high/regular perf cores options

Added high/regular performance core pinning configuration options
that can be used in place of the existing 'config' option.

'--high-perf-cores CORELIST' option allow the user to specify a
high performance cores list; if this option is not used and the
'perf-config' option is used, the application will query the
system using the rte_power library in order to get a list of
available high performance cores. The cores that are considered
high performance are the cores that have turbo enabled.

'--perf-config (port,queue,hi_perf,lcore_index)'
option is similar to the existing config option, the cores are specified
as indices for bins containing high or regular performance cores.

Example:

l3fwd-power -l 6,7 -- -p 0xff \
--high-perf-cores 6 --perf-config="(0,0,0,0),(1,0,1,0)"

cores 6 and 7 are used, core 6 is specified as a high performance core.
port 0 queue 0 will use a regular performance core, index 0 (core 7)
port 1 queue 0 will use a high performance core, index 0 (core 6)

Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Acked-by: David Hunt <david.hunt@intel.com>

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