bus/pci: make driver-only headers private

The pci bus interface is for drivers only.
Mark as internal and move the header in the driver headers list.

While at it, cleanup the code:
- fix indentatio

bus/pci: make driver-only headers private

The pci bus interface is for drivers only.
Mark as internal and move the header in the driver headers list.

While at it, cleanup the code:
- fix indentation,
- remove unneeded reference to bus specific singleton object,
- remove unneeded list head structure type,
- reorder the definitions and macro manipulating the bus singleton object,
- remove inclusion of rte_bus.h and fix the code that relied on implicit
inclusion,

Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Rosen Xu <rosen.xu@intel.com>

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raw/ntb: add PPD status check for Sapphire Rapids

Add PPD (PCIe Port Definition) status check for SPR (Sapphire Rapids).

Note that NTB on SPR has the same device id with that on ICX, while
the fiel

raw/ntb: add PPD status check for Sapphire Rapids

Add PPD (PCIe Port Definition) status check for SPR (Sapphire Rapids).

Note that NTB on SPR has the same device id with that on ICX, while
the field offsets of PPD Control Register are different. Here, we use
the PCI device revision id to distinguish the HW platform (ICX/SPR)
and check the Port Config Status and Port Definition accordingly.

+---------------------------+--------------------+--------------------+
| Fields | Bit Range (on ICX) | Bit Range (on SPR) |
+---------------------------+--------------------+--------------------+
| Port Configuration Status | 12 | 14 |
| Port Definition | 9:8 | 10:8 |
+---------------------------+--------------------+--------------------+

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>

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raw/ntb: check memory allocations

This patch adds checking for rte_zmalloc() result when init Intel ntb
device, also fix the same bug when start ntb device.

Fixes: 034c328eb025 ("raw/ntb: support I

raw/ntb: check memory allocations

This patch adds checking for rte_zmalloc() result when init Intel ntb
device, also fix the same bug when start ntb device.

Fixes: 034c328eb025 ("raw/ntb: support Intel NTB")
Fixes: c39d1e082a4b ("raw/ntb: setup queues")
Cc: stable@dpdk.org

Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
Acked-by: Xiaoyun Li <xiaoyun.li@intel.com>

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raw/ntb: support Intel Ice Lake

Add NTB device support (4th generation) for Intel Ice Lake platform.

Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>

raw/ntb: add enqueue and dequeue functions

Introduce enqueue and dequeue functions to support packet based
processing. And enable write-combining for ntb driver since it
can improve the performance

raw/ntb: add enqueue and dequeue functions

Introduce enqueue and dequeue functions to support packet based
processing. And enable write-combining for ntb driver since it
can improve the performance a lot.

Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>

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raw/ntb: setup queues

Setup and init NTB txq and rxq. And negotiate queue information
with the peer. If queue size and number of queues are not
consistent on both sides, return error.

Signed-off-by

raw/ntb: setup queues

Setup and init NTB txq and rxq. And negotiate queue information
with the peer. If queue size and number of queues are not
consistent on both sides, return error.

Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>

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raw/ntb: support Intel NTB

Add in the list of registers for the device.
And enable NTB device ops for Intel Skylake platform.

Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Acked-by: Jingjing Wu

raw/ntb: support Intel NTB

Add in the list of registers for the device.
And enable NTB device ops for Intel Skylake platform.

Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>
Reviewed-by: Xiaolong Ye <xiaolong.ye@intel.com>

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