net/ntnic: migrate to DPDK spinlock

Migrate form the pthread to rte_spinlock

Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>

net/ntnic: add flow matcher (FLM) flow module

The Flow Matcher module is a high-performance stateful SDRAM lookup
and programming engine which supported exact match lookup
in line-rate of up to hund

net/ntnic: add flow matcher (FLM) flow module

The Flow Matcher module is a high-performance stateful SDRAM lookup
and programming engine which supported exact match lookup
in line-rate of up to hundreds of millions of flows.

Signed-off-by: Oleksandr Kolomeiets <okl-plv@napatech.com>
Acked-by: Serhii Iliushyk <sil-plv@napatech.com>

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net/ntnic: extend and fix logging

Add suffixes logging
Fix the issue with the configuration log level for a specific module
Fix extended debug logging
3-letter abbreviation for log type
Upda

net/ntnic: extend and fix logging

Add suffixes logging
Fix the issue with the configuration log level for a specific module
Fix extended debug logging
3-letter abbreviation for log type
Update documentation
new log modules were added
Log level in functions that initialize feature operations
was updated from INFO to DEBUG to avoid noisy traces
during driver startup.
log level for ops init was changed
nim and PMD modules was replaced with NTNIC
NIM module was replaced with NTNIC according to the ntnic log
convention.

Signed-off-by: Oleksandr Kolomeiets <okl-plv@napatech.com>
Signed-off-by: Danylo Vodopianov <dvo-plv@napatech.com>
Acked-by: Serhii Iliushyk <sil-plv@napatech.com>

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net/ntnic: add FPGA modules for initialization

New ntnic FPGA modules:
- Host Interface (HIF): Basic FPGA info such as prod ID and build time.
- Inter-Integrated Circuit Controller (IIC): Use the FP

net/ntnic: add FPGA modules for initialization

New ntnic FPGA modules:
- Host Interface (HIF): Basic FPGA info such as prod ID and build time.
- Inter-Integrated Circuit Controller (IIC): Use the FPGA to access
the other integrated circuits on the ntnic.
- PCI Express Gen3 (PCIE3): The FPGA part of PCIe3 initialization,
speed tests, and configuration.

Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@amd.com>

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