#
ac8415cf |
| 09-Jul-2024 |
Erez Shitrit <erezsh@nvidia.com> |
net/mlx5/hws: set E-Switch owner VHC ID valid
eswitch_owner_vhca_id_valid value should be set to 1 only on merged-eswitch device.
Signed-off-by: Erez Shitrit <erezsh@nvidia.com> Acked-by: Matan Azr
net/mlx5/hws: set E-Switch owner VHC ID valid
eswitch_owner_vhca_id_valid value should be set to 1 only on merged-eswitch device.
Signed-off-by: Erez Shitrit <erezsh@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
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2e3fa232 |
| 06-May-2024 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5/hws: remove unused capabilities and fields
The following caps were never in use: - wire_regc - metadata_c - metadata_c_mask Also send ring's reg_addr field wasn't in use.
Removing these
net/mlx5/hws: remove unused capabilities and fields
The following caps were never in use: - wire_regc - metadata_c - metadata_c_mask Also send ring's reg_addr field wasn't in use.
Removing these caps and fields from structs and removing the code that queried them.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
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a5230507 |
| 26-Feb-2024 |
Hamdan Igbaria <hamdani@nvidia.com> |
net/mlx5/hws: support comparison matcher
Add support for compare matcher, this matcher will allow direct comparison between two packet fields, or a packet field and a value, with fully masked DW. Fo
net/mlx5/hws: support comparison matcher
Add support for compare matcher, this matcher will allow direct comparison between two packet fields, or a packet field and a value, with fully masked DW. For now this matcher hash table is limited to size 1x1, thus it supports only 1 rule STE.
Signed-off-by: Hamdan Igbaria <hamdani@nvidia.com> Signed-off-by: Michael Baum <michaelba@nvidia.com> Acked-by: Suanming Mou <suanmingm@nvidia.com>
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525ac5ef |
| 18-Feb-2024 |
Hamdan Igbaria <hamdani@nvidia.com> |
net/mlx5/hws: support ESP push for insert header action
support push_esp flag for insert header action, it must be set when inserting an ESP header, it's also sets the next_protocol field in the IPs
net/mlx5/hws: support ESP push for insert header action
support push_esp flag for insert header action, it must be set when inserting an ESP header, it's also sets the next_protocol field in the IPsec trailer.
Signed-off-by: Hamdan Igbaria <hamdani@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
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2acdf09b |
| 13-Feb-2024 |
Hamdan Igbaria <hamdani@nvidia.com> |
net/mlx5/hws: add encap entropy hash calculation
Add new function for encap entropy hash calculation, the function will check the device capability for the entropy hash type used by the device, and
net/mlx5/hws: add encap entropy hash calculation
Add new function for encap entropy hash calculation, the function will check the device capability for the entropy hash type used by the device, and will calculate the entropy hash value of the user passed fields according this type.
Signed-off-by: Hamdan Igbaria <hamdani@nvidia.com> Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
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bbddd062 |
| 01-Nov-2023 |
Alex Vesker <valex@nvidia.com> |
net/mlx5/hws: add dynamic re-parsing of packet
Each steering entry (STE) has a bit called re-parse used for re-parsing the packet in HW, re-parsing is needed after reformat (e.g. push/pop/encapsulat
net/mlx5/hws: add dynamic re-parsing of packet
Each steering entry (STE) has a bit called re-parse used for re-parsing the packet in HW, re-parsing is needed after reformat (e.g. push/pop/encapsulate/...) or when modifying the packet headers requiring structure change (e.g. TCP to UDP). Until now we re-parsed the packet in each STE leading to longer processing per packet. With supported devices we can control re-parse bit to allow better performance.
Signed-off-by: Alex Vesker <valex@nvidia.com> Reviewed-by: Erez Shitrit <erezsh@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
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1f8fc88d |
| 01-Nov-2023 |
Alex Vesker <valex@nvidia.com> |
net/mlx5/hws: allow jump to TIR over FDB
Current TIR action is allowed to be used only for NIC RX, this will allow TIR action over FDB for RX traffic in case of TX traffic packets will be dropped.
net/mlx5/hws: allow jump to TIR over FDB
Current TIR action is allowed to be used only for NIC RX, this will allow TIR action over FDB for RX traffic in case of TX traffic packets will be dropped.
Signed-off-by: Alex Vesker <valex@nvidia.com> Reviewed-by: Erez Shitrit <erezsh@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
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7f5e6de5 |
| 29-Oct-2023 |
Itamar Gozlan <igozlan@nvidia.com> |
net/mlx5/hws: query flow rule hash
Add a method to the HW steering API that allows querying the hash result for a given matcher and a set of items. This can be used to predict the location of the ru
net/mlx5/hws: query flow rule hash
Add a method to the HW steering API that allows querying the hash result for a given matcher and a set of items. This can be used to predict the location of the rule in the hash table.
Signed-off-by: Itamar Gozlan <igozlan@nvidia.com> Acked-by: Ori Kam <orika@nvidia.com> Acked-by: Suanming Mou <suanmingm@nvidia.com>
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#
71ad5095 |
| 26-Oct-2023 |
Haifei Luo <haifeil@nvidia.com> |
net/mlx5/hws: support reformat action for mirror
In dest_array action, an optional reformat action can be applied to each destination. This patch supports this by using the extended destination entr
net/mlx5/hws: support reformat action for mirror
In dest_array action, an optional reformat action can be applied to each destination. This patch supports this by using the extended destination entry.
Signed-off-by: Haifei Luo <haifeil@nvidia.com> Signed-off-by: Shun Hao <shunh@nvidia.com> Acked-by: Suanming Mou <suanmingm@nvidia.com>
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eefaf43d |
| 26-Oct-2023 |
Shun Hao <shunh@nvidia.com> |
net/mlx5/hws: support mirroring
This patch supports mirroring by adding an dest_array action. The action accecpts a list containing multiple destination actions, and can duplicate packet and forward
net/mlx5/hws: support mirroring
This patch supports mirroring by adding an dest_array action. The action accecpts a list containing multiple destination actions, and can duplicate packet and forward to each destination in the list.
Signed-off-by: Shun Hao <shunh@nvidia.com> Acked-by: Alex Vesker <valex@nvidia.com> Acked-by: Suanming Mou <suanmingm@nvidia.com>
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2b2ce5dd |
| 26-Oct-2023 |
Hamdan Igbaria <hamdani@nvidia.com> |
net/mlx5/hws: support dynamic forward table and FTE
Add the ability to create forward table and FTE.
Signed-off-by: Hamdan Igbaria <hamdani@nvidia.com> Acked-by: Suanming Mou <suanmingm@nvidia.com>
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25cb2d2a |
| 26-Oct-2023 |
Hamdan Igbaria <hamdani@nvidia.com> |
net/mlx5/hws: support reformat DevX object
Add support for creation of packet reformat object, via the ALLOC_PACKET_REFORMAT_CONTEXT command.
Signed-off-by: Hamdan Igbaria <hamdani@nvidia.com> Acke
net/mlx5/hws: support reformat DevX object
Add support for creation of packet reformat object, via the ALLOC_PACKET_REFORMAT_CONTEXT command.
Signed-off-by: Hamdan Igbaria <hamdani@nvidia.com> Acked-by: Suanming Mou <suanmingm@nvidia.com>
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b81f95ca |
| 18-Sep-2023 |
Itamar Gozlan <igozlan@nvidia.com> |
net/mlx5/hws: support default miss table
A default miss table is a way to define what happens to traffic that does not match any rule in a specific table. In hws, this is done by connecting the sour
net/mlx5/hws: support default miss table
A default miss table is a way to define what happens to traffic that does not match any rule in a specific table. In hws, this is done by connecting the source table to the target table using the RTC. This ensures that traffic that does not match any rule in the source table is forwarded to the target table.
Signed-off-by: Itamar Gozlan <igozlan@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
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e1df1578 |
| 20-Mar-2023 |
Hamdan Igbaria <hamdani@nvidia.com> |
net/mlx5/hws: enhance forward table and FTE creation
Changed FW FT and FTE creation to allow dynamic creation. Till now only FTE with vport destination action was supported. Also enhanced forward ta
net/mlx5/hws: enhance forward table and FTE creation
Changed FW FT and FTE creation to allow dynamic creation. Till now only FTE with vport destination action was supported. Also enhanced forward table creation to be generic.
Signed-off-by: Hamdan Igbaria <hamdani@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
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004edb48 |
| 20-Mar-2023 |
Hamdan Igbaria <hamdani@nvidia.com> |
net/mlx5/hws: dump FT ICM addresses
Add the support for query FT command. Use the query FT command to dump the ICM addresses of table start anchor and matcher end anchor.
Signed-off-by: Hamdan Igba
net/mlx5/hws: dump FT ICM addresses
Add the support for query FT command. Use the query FT command to dump the ICM addresses of table start anchor and matcher end anchor.
Signed-off-by: Hamdan Igbaria <hamdani@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
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81cf20a2 |
| 13-Feb-2023 |
Hamdan Igbaria <hamdani@nvidia.com> |
net/mlx5/hws: support match on ESP item
Add the support to match on SPI and sequence number fields of ESP header.
The match on ESP header in hardware steering is supported only if firmware reports
net/mlx5/hws: support match on ESP item
Add the support to match on SPI and sequence number fields of ESP header.
The match on ESP header in hardware steering is supported only if firmware reports the device supports IPsec offload.
Signed-off-by: Hamdan Igbaria <hamdani@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
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93ee3bd8 |
| 01-Feb-2023 |
Alex Vesker <valex@nvidia.com> |
net/mlx5/hws: align RTC create command with PRM format
Rename rtc params create for new format.
Signed-off-by: Alex Vesker <valex@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
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67acee3a |
| 01-Feb-2023 |
Alex Vesker <valex@nvidia.com> |
net/mlx5/hws: add capability query for generate WQE
Read the capabilities required to determine support for GENERATE_WQE.
Signed-off-by: Alex Vesker <valex@nvidia.com> Acked-by: Matan Azrad <matan@
net/mlx5/hws: add capability query for generate WQE
Read the capabilities required to determine support for GENERATE_WQE.
Signed-off-by: Alex Vesker <valex@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
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12802ab2 |
| 01-Feb-2023 |
Alex Vesker <valex@nvidia.com> |
net/mlx5/hws: support GTA WQE write using FW command
The generate WQE command is used as an interface to writing GTA WQEs with fields that are not supported in current HW, for example extended match
net/mlx5/hws: support GTA WQE write using FW command
The generate WQE command is used as an interface to writing GTA WQEs with fields that are not supported in current HW, for example extended match definer.
Signed-off-by: Alex Vesker <valex@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
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51f68dba |
| 12-Jan-2023 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5/hws: read capabilities for split and linear tables
Read device capabilities that describe the support for Hash Split table and Linear RTC table.
Signed-off-by: Yevgeny Kliteynik <kliteyn@n
net/mlx5/hws: read capabilities for split and linear tables
Read device capabilities that describe the support for Hash Split table and Linear RTC table.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
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07f35716 |
| 12-Jan-2023 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5/hws: add hash split and linear lookup tables
Added PRM bits for new RTC types: Hash Split and Linear Lookup tables, as well as for HASH_RESULT field that contains hash result of the Hash Sp
net/mlx5/hws: add hash split and linear lookup tables
Added PRM bits for new RTC types: Hash Split and Linear Lookup tables, as well as for HASH_RESULT field that contains hash result of the Hash Split table calculation.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
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ce946c7d |
| 05-Jan-2023 |
Erez Shitrit <erezsh@nvidia.com> |
net/mlx5/hws: support ibv context shared with local one
The idea is to have a shared ibv_context that all the resources allocated on it (FT + TIR are exceptions) Whenever a resource is created local
net/mlx5/hws: support ibv context shared with local one
The idea is to have a shared ibv_context that all the resources allocated on it (FT + TIR are exceptions) Whenever a resource is created locally an alias object to that resource allocated and used in the other context. The connections between the resources are done according to each type of the resource, to the original resource, or its alias resource.
Signed-off-by: Erez Shitrit <erezsh@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
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7ab100f6 |
| 05-Jan-2023 |
Erez Shitrit <erezsh@nvidia.com> |
net/mlx5/hws: add VHCA identifier to the capabilities
This adds the vhca identifier ids, that is read by query_cap function.
Signed-off-by: Erez Shitrit <erezsh@nvidia.com> Reviewed-by: Alex Vesker
net/mlx5/hws: add VHCA identifier to the capabilities
This adds the vhca identifier ids, that is read by query_cap function.
Signed-off-by: Erez Shitrit <erezsh@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
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#
ed695274 |
| 05-Jan-2023 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5/hws: add command to create alias objects
Added support for a command that can create alias objects - objects that are accessed across VHCA.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia
net/mlx5/hws: add command to create alias objects
Added support for a command that can create alias objects - objects that are accessed across VHCA.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
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720439d8 |
| 05-Jan-2023 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5/hws: add other VHCA access
Added FW command to allow creation of alias objects.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Acked-by:
net/mlx5/hws: add other VHCA access
Added FW command to allow creation of alias objects.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
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