| 68508c18 | 14-Nov-2024 |
Hemant Agrawal <hemant.agrawal@nxp.com> |
bus/dpaa: enable clang thread safety check for FQ locks
Enable "annotate_locks" for compile-time checks by clang.
FQLOCK and FQUNLOCK need to be considered as lock functions that the clang analyzer
bus/dpaa: enable clang thread safety check for FQ locks
Enable "annotate_locks" for compile-time checks by clang.
FQLOCK and FQUNLOCK need to be considered as lock functions that the clang analyzer can rely on.
Signed-off-by: David Marchand <david.marchand@redhat.com> Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
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| 051f4185 | 23-Oct-2024 |
Rohit Raj <rohit.raj@nxp.com> |
bus/fslmc: fix Coverity warnings in QBMAN
Fix Issues reported by NXP Internal Coverity.
Fixes: 64f131a82fbe ("bus/fslmc: add qbman debug") Cc: stable@dpdk.org
Signed-off-by: Rohit Raj <rohit.raj@n
bus/fslmc: fix Coverity warnings in QBMAN
Fix Issues reported by NXP Internal Coverity.
Fixes: 64f131a82fbe ("bus/fslmc: add qbman debug") Cc: stable@dpdk.org
Signed-off-by: Rohit Raj <rohit.raj@nxp.com> Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
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| a3c123e2 | 23-Oct-2024 |
Jun Yang <jun.yang@nxp.com> |
bus/fslmc: make IOVA mode configuration dynamic
IOVA mode should not be configured with CFLAGS because 1) User can perform "--iova-mode" to configure IOVA. 2) IOVA mode is determined by negotiation
bus/fslmc: make IOVA mode configuration dynamic
IOVA mode should not be configured with CFLAGS because 1) User can perform "--iova-mode" to configure IOVA. 2) IOVA mode is determined by negotiation between multiple devices. Eal is in VA mode only when all devices support VA mode.
Hence: 1) Remove RTE_LIBRTE_DPAA2_USE_PHYS_IOVA cflags. Instead, use rte_eal_iova_mode API to identify VA or PA mode. 2) Support memory IOMMU mapping and I/O IOMMU mapping(PCI space). 3) For memory IOMMU, in VA mode, IOVA:VA = 1:1; in PA mode, IOVA:VA = PA:VA. The mapping policy is determined by EAL memory driver. 4) For I/O IOMMU, IOVA:VA is up to I/O driver configuration. In general, it's aligned with memory IOMMU mapping. 5) Memory and I/O IOVA tables are created and update when DMA mapping is setup, which takes place of dpaax IOVA table.
Signed-off-by: Jun Yang <jun.yang@nxp.com> Signed-off-by: Vanshika Shukla <vanshika.shukla@nxp.com> Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
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| 3b5f8dfa | 23-Oct-2024 |
Rohit Raj <rohit.raj@nxp.com> |
bus/fslmc: free VFIO group FD on group add failure
Free vfio_group_fd if add group fails to avoid resource leak
Signed-off-by: Rohit Raj <rohit.raj@nxp.com> Acked-by: Hemant Agrawal <hemant.agrawal
bus/fslmc: free VFIO group FD on group add failure
Free vfio_group_fd if add group fails to avoid resource leak
Signed-off-by: Rohit Raj <rohit.raj@nxp.com> Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
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| 57cb02ed | 23-Oct-2024 |
Jun Yang <jun.yang@nxp.com> |
bus/fslmc: enhance MC VFIO multi-process support
MC VFIO is not registered into RTE VFIO. Primary process registers MC vfio mp action for secondary process to request. VFIO/Container handlers are pr
bus/fslmc: enhance MC VFIO multi-process support
MC VFIO is not registered into RTE VFIO. Primary process registers MC vfio mp action for secondary process to request. VFIO/Container handlers are provided via CMSG. Primary process is responsible to connect MC VFIO group to container.
In addition, MC VFIO code is refactored according to container/group logic. In general, VFIO container can support multiple groups per process. Now we only support single MC group(dprc.x) per process, but we add logic to support connecting multiple MC groups to container.
Signed-off-by: Jun Yang <jun.yang@nxp.com> Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
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| 0e603d80 | 23-Oct-2024 |
Jun Yang <jun.yang@nxp.com> |
bus/fslmc: get MC VFIO group FD directly
Get vfio group fd directly from file system instead of from RTE API to avoid conflicting with PCIe VFIO. FSL MC VFIO should have it's own logic which doe NOT
bus/fslmc: get MC VFIO group FD directly
Get vfio group fd directly from file system instead of from RTE API to avoid conflicting with PCIe VFIO. FSL MC VFIO should have it's own logic which doe NOT depend on RTE VFIO.
Signed-off-by: Jun Yang <jun.yang@nxp.com> Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
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