lib: replace packed attributes

MSVC struct packing is not compatible with GCC. Replace macro
__rte_packed with __rte_packed_begin to push existing pack value
and set packing to 1-byte and macro __rt

lib: replace packed attributes

MSVC struct packing is not compatible with GCC. Replace macro
__rte_packed with __rte_packed_begin to push existing pack value
and set packing to 1-byte and macro __rte_packed_end to restore
the pack value prior to the push.

Macro __rte_packed_end is deliberately utilized to trigger a
MSVC compiler warning if no existing packing has been pushed allowing
easy identification of locations where the __rte_packed_begin is
missing.

Signed-off-by: Andre Muezerie <andremue@linux.microsoft.com>

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doc: reorganize prog guide

Create categories in the index of the programmer's guide,
sort chapters and rewrite some titles for consistency.

Subdirectories are created for ethdev and eventdev
for gr

doc: reorganize prog guide

Create categories in the index of the programmer's guide,
sort chapters and rewrite some titles for consistency.

Subdirectories are created for ethdev and eventdev
for grouping the files together.

Useless link anchors at the beginning of files are removed,
the corresponding :ref: are replaced with :doc: links.

Signed-off-by: David Young <dave@youngcopy.com>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>

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acl: check max SIMD bitwidth

When choosing a vector path to take, an extra condition must be
satisfied to ensure the max SIMD bitwidth allows for the CPU enabled
path. These checks are added in the

acl: check max SIMD bitwidth

When choosing a vector path to take, an extra condition must be
satisfied to ensure the max SIMD bitwidth allows for the CPU enabled
path. These checks are added in the check alg helper functions.

Signed-off-by: Ciara Power <ciara.power@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Tested-by: Konstantin Ananyev <konstantin.ananyev@intel.com>

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acl: add 512-bit AVX512 classify method

Introduce classify implementation that uses AVX512 specific ISA.
rte_acl_classify_avx512x32() is able to process up to 32 flows in parallel.
It uses 512-bit w

acl: add 512-bit AVX512 classify method

Introduce classify implementation that uses AVX512 specific ISA.
rte_acl_classify_avx512x32() is able to process up to 32 flows in parallel.
It uses 512-bit width registers/instructions and provides higher
performance then rte_acl_classify_avx512x16(), but can cause
frequency level change.
Note that for now only 64-bit version is supported.

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>

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acl: add 256-bit AVX512 classify method

Introduce classify implementation that uses AVX512 specific ISA.
rte_acl_classify_avx512x16() is able to process up to 16 flows in parallel.
It uses 256-bit w

acl: add 256-bit AVX512 classify method

Introduce classify implementation that uses AVX512 specific ISA.
rte_acl_classify_avx512x16() is able to process up to 16 flows in parallel.
It uses 256-bit width registers/instructions only
(to avoid frequency level change).
Note that for now only 64-bit version is supported.

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>

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doc: fix missing classify methods in ACL guide

Add brief description for missing ACL classify algorithms:
RTE_ACL_CLASSIFY_NEON and RTE_ACL_CLASSIFY_ALTIVEC.

Fixes: 34fa6c27c156 ("acl: add NEON opt

doc: fix missing classify methods in ACL guide

Add brief description for missing ACL classify algorithms:
RTE_ACL_CLASSIFY_NEON and RTE_ACL_CLASSIFY_ALTIVEC.

Fixes: 34fa6c27c156 ("acl: add NEON optimization for ARMv8")
Fixes: 1d73135f9f1c ("acl: add AltiVec for ppc64")
Cc: stable@dpdk.org

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>

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replace packed attributes

There is a common macro __rte_packed for packing structs,
which is now used where appropriate for consistency.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>

doc/guides: clean repeated words

Shoot repeated words in all our guides.

Cc: stable@dpdk.org

Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Kevin Traynor <ktraynor@redhat.com>

net: replace IPv4/v6 constants with uppercase name

Since we change these macros, we might as well avoid triggering complaints
from checkpatch because of mixed case.

old=RTE_IPv4
new=RTE_IPV4
git gr

net: replace IPv4/v6 constants with uppercase name

Since we change these macros, we might as well avoid triggering complaints
from checkpatch because of mixed case.

old=RTE_IPv4
new=RTE_IPV4
git grep -lw $old | xargs sed -i -e "s/\<$old\>/$new/g"

old=RTE_ETHER_TYPE_IPv4
new=RTE_ETHER_TYPE_IPV4
git grep -lw $old | xargs sed -i -e "s/\<$old\>/$new/g"

old=RTE_ETHER_TYPE_IPv6
new=RTE_ETHER_TYPE_IPV6
git grep -lw $old | xargs sed -i -e "s/\<$old\>/$new/g"

Signed-off-by: David Marchand <david.marchand@redhat.com>
Reviewed-by: Olivier Matz <olivier.matz@6wind.com>

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net: add rte prefix to IP defines

Add 'RTE_' prefix to defines:
- rename IPv4( as RTE_IPv4(.
- rename IPV4_MAX_PKT_LEN as RTE_IPV4_MAX_PKT_LEN.
- rename IPV4_HDR_IHL_MASK as RTE_IPV4_HDR_IHL_MASK.
-

net: add rte prefix to IP defines

Add 'RTE_' prefix to defines:
- rename IPv4( as RTE_IPv4(.
- rename IPV4_MAX_PKT_LEN as RTE_IPV4_MAX_PKT_LEN.
- rename IPV4_HDR_IHL_MASK as RTE_IPV4_HDR_IHL_MASK.
- rename IPV4_IHL_MULTIPLIER as RTE_IPV4_IHL_MULTIPLIER.
- rename IPV4_HDR_DF_SHIFT as RTE_IPV4_HDR_DF_SHIFT.
- rename IPV4_HDR_MF_SHIFT as RTE_IPV4_HDR_MF_SHIFT.
- rename IPV4_HDR_FO_SHIFT as RTE_IPV4_HDR_FO_SHIFT.
- rename IPV4_HDR_DF_FLAG as RTE_IPV4_HDR_DF_FLAG.
- rename IPV4_HDR_MF_FLAG as RTE_IPV4_HDR_MF_FLAG.
- rename IPV4_HDR_OFFSET_MASK as RTE_IPV4_HDR_OFFSET_MASK.
- rename IPV4_HDR_OFFSET_UNITS as RTE_IPV4_HDR_OFFSET_UNITS.
- rename IPV4_ANY as RTE_IPV4_ANY.
- rename IPV4_LOOPBACK as RTE_IPV4_LOOPBACK.
- rename IPV4_BROADCAST as RTE_IPV4_BROADCAST.
- rename IPV4_ALLHOSTS_GROUP as RTE_IPV4_ALLHOSTS_GROUP.
- rename IPV4_ALLRTRS_GROUP as RTE_IPV4_ALLRTRS_GROUP.
- rename IPV4_MAX_LOCAL_GROUP as RTE_IPV4_MAX_LOCAL_GROUP.
- rename IPV4_MIN_MCAST as RTE_IPV4_MIN_MCAST.
- rename IPV4_MAX_MCAST as RTE_IPV4_MAX_MCAST.
- rename IS_IPV4_MCAST as RTE_IS_IPV4_MCAST.
- rename IPV6_HDR_FL_SHIFT as RTE_IPV6_HDR_FL_SHIFT.
- rename IPV6_HDR_TC_SHIFT as RTE_IPV6_HDR_TC_SHIFT.
- rename IPV6_HDR_FL_MASK as RTE_IPV6_HDR_FL_MASK.
- rename IPV6_HDR_TC_MASK as RTE_IPV6_HDR_TC_MASK.

Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
Reviewed-by: Stephen Hemminger <stephen@networkplumber.org>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

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net: add rte prefix to IP structure

Add 'rte_' prefix to structures:
- rename struct ipv4_hdr as struct rte_ipv4_hdr.
- rename struct ipv6_hdr as struct rte_ipv6_hdr.

Signed-off-by: Olivier Matz <o

net: add rte prefix to IP structure

Add 'rte_' prefix to structures:
- rename struct ipv4_hdr as struct rte_ipv4_hdr.
- rename struct ipv6_hdr as struct rte_ipv6_hdr.

Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
Reviewed-by: Stephen Hemminger <stephen@networkplumber.org>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

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doc: convert Intel license headers to SPDX tags

Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>

acl: allow zero verdict

This enables ACL matches to return 0 where the distinction
from no-match case is not needed.

Signed-off-by: Michał Mirosław <michal.miroslaw@atendesoftware.pl>
Acked-by: Kon

acl: allow zero verdict

This enables ACL matches to return 0 where the distinction
from no-match case is not needed.

Signed-off-by: Michał Mirosław <michal.miroslaw@atendesoftware.pl>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>

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doc: add a further example in ACL guide

Add a further ACL example where the elements of the search key
are not entirely fitting into the 4 consecutive bytes of all
input fields.

Signed-off-by: Anto

doc: add a further example in ACL guide

Add a further ACL example where the elements of the search key
are not entirely fitting into the 4 consecutive bytes of all
input fields.

Signed-off-by: Antonio Fischetti <antonio.fischetti@intel.com>
Acked-by: John McNamara <john.mcnamara@intel.com>

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doc: fix spellings and typos

Fixed several typos and spelling errors in guide docs.

Signed-off-by: John McNamara <john.mcnamara@intel.com>

doc: describe ACL memory size build parameter

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Siobhan Butler <siobhan.a.butler@intel.com>

doc: describe ACL classification methods

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Siobhan Butler <siobhan.a.butler@intel.com>

doc: add restrictions for ACL rule fields

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Siobhan Butler <siobhan.a.butler@intel.com>

doc: remove Intel references from prog guide

Removed redundant references to Intel(R) DPDK in Programmers Guide.

Signed-off-by: Siobhan Butler <siobhan.a.butler@intel.com>
Acked-by: Bernard Iremong

doc: remove Intel references from prog guide

Removed redundant references to Intel(R) DPDK in Programmers Guide.

Signed-off-by: Siobhan Butler <siobhan.a.butler@intel.com>
Acked-by: Bernard Iremonger <bernard.iremonger@intel.com>

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doc: programmers guide

The 1.7 DPDK_Prog_Guide document in MSWord has been converted to rst format for
use with Sphinx. There is an rst file for each chapter and an index.rst file
which contains the

doc: programmers guide

The 1.7 DPDK_Prog_Guide document in MSWord has been converted to rst format for
use with Sphinx. There is an rst file for each chapter and an index.rst file
which contains the table of contents.
The top level index file has been modified to include this guide.

This document contains some png image files. If any of these png files are modified
they should be replaced with an svg file.

This is the sixth document from a set of 6 documents.

Signed-off-by: Bernard Iremonger <bernard.iremonger@intel.com>

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