| 8c53b9b7 | 15-Oct-2024 |
Jun Yang <jun.yang@nxp.com> |
dma/dpaa: add QDMA stall workaround for ERR050265
Non-prefetchable read setting in the source descriptor may be
required for targets other than local memory. Prefetchable read
setting will offer bet
dma/dpaa: add QDMA stall workaround for ERR050265
Non-prefetchable read setting in the source descriptor may be
required for targets other than local memory. Prefetchable read
setting will offer better performance for misaligned transfers
in the form of fewer transactions and should be set if possible.
This patch also fixes QDMA stall issue due to unaligned
transactions.
Signed-off-by: Jun Yang <jun.yang@nxp.com>
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
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| bdcb782a | 15-Oct-2024 |
Jun Yang <jun.yang@nxp.com> |
dma/dpaa: add workaround for ERR050757
ERR050757 on LS104x indicates:
For outbound PCIe read transactions, a completion buffer is used
to store the PCIe completions till the data is passed back to
dma/dpaa: add workaround for ERR050757
ERR050757 on LS104x indicates:
For outbound PCIe read transactions, a completion buffer is used
to store the PCIe completions till the data is passed back to the
initiator. At most 16 outstanding transactions are allowed and
maximum read request is 256 bytes. The completion buffer size
inside the controller needs to be at least 4KB, but the PCIe
controller has 3 KB of buffer. In case the size of pending
outbound read transactions of more than 3KB, the PCIe controller
may drop the incoming completions without notifying the initiator
of the transaction, leaving transactions unfinished. All
subsequent outbound reads to PCIe are blocked permanently.
To avoid qDMA hang as it keeps waiting for data that was silently
dropped, set stride mode for qDMA.
Signed-off-by: Jun Yang <jun.yang@nxp.com>
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
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| 9e2f8ca6 | 05-May-2022 |
Nipun Gupta <nipun.gupta@nxp.com> |
dma/dpaa2: support DMA operations
This patch support copy, submit, completed and
completed status functionality of DMA driver.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Acked-by: Hemant Agra
dma/dpaa2: support DMA operations
This patch support copy, submit, completed and
completed status functionality of DMA driver.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
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| 7a8a886f | 16-Feb-2022 |
Bruce Richardson <bruce.richardson@intel.com> |
doc: improve configuration examples in idxd guide
The documentation on how to configure device instances using
accel-config can be improved by a number of changes:
* For initial example, when only
doc: improve configuration examples in idxd guide
The documentation on how to configure device instances using
accel-config can be improved by a number of changes:
* For initial example, when only configuring one queue, omit
configuration of a second engine, which is unused later.
* Add the "max-batch-size" setting to the options being configured for
each queue
* Add a final, more complete example, showing configuration of multiple
queues on a device.
Cc: stable@dpdk.org
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: Kevin Laatz <kevin.laatz@intel.com>
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| 03390445 | 17-Feb-2022 |
Chengwen Feng <fengchengwen@huawei.com> |
dma/hisilicon: use common PCI device naming
For DMA device 0000:7d:0.0, the original generated dmadev name starts
with the "7d:0.0", which is not expected.
This patch uses rte_pci_device_name API to
dma/hisilicon: use common PCI device naming
For DMA device 0000:7d:0.0, the original generated dmadev name starts
with the "7d:0.0", which is not expected.
This patch uses rte_pci_device_name API to generates the dmadev name.
Cc: stable@dpdk.org
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
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| 9e16317a | 02-Nov-2021 |
Chengwen Feng <fengchengwen@huawei.com> |
dma/hisilicon: add probing
This patch add dmadev instances create during the PCI probe, and
destroy them during the PCI remove. Internal structures and HW
definitions was also included.
Signed-off-
dma/hisilicon: add probing
This patch add dmadev instances create during the PCI probe, and
destroy them during the PCI remove. Internal structures and HW
definitions was also included.
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
show more ...
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